usrp2-xcvr cleanup, working gains, freqs

git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10387 221aa14e-8319-0410-a670-987f0aec2ac5

1 files changed, 154 insertions, 158 deletions

diff --git a/usrp2/firmware/lib/db_xcvr2450.c b/usrp2/firmware/lib/db_xcvr2450.c
index d2e96a3e6..6c165bc96 100644
--- a/usrp2/firmware/lib/db_xcvr2450.c
+++ b/usrp2/firmware/lib/db_xcvr2450.c
@@ -52,9 +52,12 @@ void set_atr_regs(int bank, struct db_base *db); //FIXME I need to be in a heade
 #define TX_SAFE_IO HB_PA_OFF|LB_PA_OFF|ANTSEL_TX1_RX2|AD9515DIV
 #define TX_ATR_MASK HB_PA_OFF|LB_PA_OFF|ANTSEL_TX1_RX2|ANTSEL_TX2_RX1|TX_EN|AD9515DIV
 
-#define TUN_FREQ_MIN U2_DOUBLE_TO_FXPT_FREQ(2.3e9)
-#define TUN_FREQ_MAX U2_DOUBLE_TO_FXPT_FREQ(6.1e9)
-#define REF_CLK_DIV 1
+#define LB_FREQ_MIN U2_DOUBLE_TO_FXPT_FREQ(2.3e9)
+#define LB_FREQ_MAX U2_DOUBLE_TO_FXPT_FREQ(2.6e9)
+#define HB_FREQ_MIN U2_DOUBLE_TO_FXPT_FREQ(4.8e9)
+#define HB_FREQ_MAX U2_DOUBLE_TO_FXPT_FREQ(6.1e9)
+#define MASTER_REF_CLK_DIV 1
+#define N_DIV_MIN_Q16 (130 << 16)
 
 bool xcvr2450_init(struct db_base *db);
 bool xcvr2450_set_freq(struct db_base *db, u2_fxpt_freq_t freq, u2_fxpt_freq_t *dc);
@@ -73,22 +76,59 @@ struct db_xcvr2450_common {
   int d_pabias_delay, d_pabias;
   int d_rx_rf_gain, d_rx_bb_gain, d_txgain;
   int d_ad9515_div;
-  int spi_mask;
+  int d_tx_enb;
 };
 
 struct db_xcvr2450_dummy {
   struct db_base base;
-  struct db_xcvr2450_common common;
+  struct db_xcvr2450_common *common;
 };
 
 struct db_xcvr2450_rx {
   struct db_base base;
-  struct db_xcvr2450_common common;
+  struct db_xcvr2450_common *common;
 };
 
 struct db_xcvr2450_tx {
   struct db_base base;
-  struct db_xcvr2450_common common;
+  struct db_xcvr2450_common *common;
+};
+
+/*
+ * shared common between rx and tx db
+ */
+struct db_xcvr2450_common db_xcvr2450_common = {
+  /* set sane defaults */
+  .d_mimo = 1,          // 0 = OFF, 1 = ON
+  .d_int_div = 192,     // 128 = min, 255 = max
+  .d_frac_div = 0,      // 0 = min, 65535 = max
+  .d_highband = 0,      // 0 = freq <= 5.4e9, 1 = freq > 5.4e9
+  .d_five_gig = 0,      // 0 = freq <= 3.e9, 1 = freq > 3e9
+  .d_cp_current = 0,    // 0 = 2mA, 1 = 4mA
+  .d_ref_div = 1,       // 1 to 7
+  .d_rssi_hbw = 0,      // 0 = 2 MHz, 1 = 6 MHz
+  .d_txlpf_bw = 1,      // 1 = 12 MHz, 2 = 18 MHz, 3 = 24 MHz
+  .d_rxlpf_bw = 1,      // 0 = 7.5 MHz, 1 = 9.5 MHz, 2 = 14 MHz, 3 = 18 MHz
+  .d_rxlpf_fine = 2,    // 0 = 90%, 1 = 95%, 2 = 100%, 3 = 105%, 4 = 110%
+  .d_rxvga_ser = 1,     // 0 = RXVGA controlled by B7:1, 1=controlled serially
+  .d_rssi_range = 1,    // 0 = low range (datasheet typo), 1=high range (0.5V - 2.0V)
+  .d_rssi_mode = 1,     // 0 = enable follows RXHP, 1 = enabled
+  .d_rssi_mux = 0,      // 0 = RSSI, 1 = TEMP
+  .d_rx_hp_pin = 0,     // 0 = Fc set by rx_hpf, 1 = 600 KHz
+  .d_rx_hpf = 0,        // 0 = 100Hz, 1 = 30KHz
+  .d_rx_ant = 0,        // 0 = Ant. #1, 1 = Ant. #2
+  .d_tx_ant = 0,        // 0 = Ant. #1, 1 = Ant. #2
+  .d_txvga_ser = 1,     // 0 = TXVGA controlled by B6:1, 1=controlled serially
+  .d_tx_driver_lin = 2, // 0=50% (worst linearity), 1=63%, 2=78%, 3=100% (best lin)
+  .d_tx_vga_lin = 2,    // 0=50% (worst linearity), 1=63%, 2=78%, 3=100% (best lin)
+  .d_tx_upconv_lin = 2, // 0=50% (worst linearity), 1=63%, 2=78%, 3=100% (best lin)
+  .d_tx_bb_gain = 3,    // 0=maxgain-5dB, 1=max-3dB, 2=max-1.5dB, 3=max
+  .d_pabias_delay = 15, // 0 = 0, 15 = 7uS
+  .d_pabias = 0,        // 0 = 0 uA, 63 = 315uA
+  .d_rx_rf_gain = 0,    // 0 = 0dB, 1 = 0dB, 2 = 15dB, 3 = 30dB
+  .d_rx_bb_gain = 16,   // 0 = min, 31 = max (0 - 62 dB)
+  .d_txgain = 63,       // 0 = min, 63 = max
+  .d_tx_enb = 1,        // 0 = disabled, 1 = enabled
 };
 
 /*
@@ -99,8 +139,8 @@ struct db_xcvr2450_rx db_xcvr2450_rx = {
   .base.is_tx = false,
   .base.output_enables = RX_OE_MASK,
   .base.used_pins = 0xFFFF,
-  .base.freq_min = TUN_FREQ_MIN,
-  .base.freq_max = TUN_FREQ_MAX,
+  .base.freq_min = LB_FREQ_MIN,
+  .base.freq_max = HB_FREQ_MAX,
   .base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(0),
   .base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(92),
   .base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(1),
@@ -113,6 +153,7 @@ struct db_xcvr2450_rx db_xcvr2450_rx = {
   .base.atr_mask = RX_ATR_MASK,
   .base.atr_txval = 0x0,
   .base.atr_rxval = 0x0,
+  .common = &db_xcvr2450_common,
 };
 
 struct db_xcvr2450_tx db_xcvr2450_tx = {
@@ -120,8 +161,8 @@ struct db_xcvr2450_tx db_xcvr2450_tx = {
   .base.is_tx = true,
   .base.output_enables = TX_OE_MASK,
   .base.used_pins = 0xFFFF,
-  .base.freq_min = TUN_FREQ_MIN,
-  .base.freq_max = TUN_FREQ_MAX,
+  .base.freq_min = LB_FREQ_MIN,
+  .base.freq_max = HB_FREQ_MAX,
   .base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(0),
   .base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(30),
   .base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(30.0/63.0),
@@ -131,66 +172,68 @@ struct db_xcvr2450_tx db_xcvr2450_tx = {
   .base.init = xcvr2450_init,
   .base.set_freq = xcvr2450_set_freq,
   .base.set_gain = xcvr2450_set_gain_tx,
+  .base.set_tx_enable = xcvr2450_set_tx_enable,
   .base.atr_mask = TX_ATR_MASK,
   .base.atr_txval = 0x0,
   .base.atr_rxval = 0x0,
+  .common = &db_xcvr2450_common,
 };
 
 /**************************************************
  * Set Registers
  **************************************************/
 static void
-send_reg(struct db_xcvr2450_dummy *db, int v){
+send_reg(int v){
   // Send 24 bits, it keeps last 18 clocked in
-  spi_transact(SPI_TXONLY,db->common.spi_mask,v,24,SPIF_PUSH_FALL);
+  spi_transact(SPI_TXONLY,SPI_SS_RX_DB,v,24,SPIF_PUSH_FALL);
   //printf("xcvr2450: Setting reg %d to %x\n", (v&15), v);
 }
 
 static void
 set_reg_standby(struct db_xcvr2450_dummy *db){
   int reg_standby = (
-    (db->common.d_mimo<<17) |
+    (db->common->d_mimo<<17) |
     (1<<16)                 |
     (1<<6)                  |
     (1<<5)                  |
     (1<<4)                  | 2);
-  send_reg(db, reg_standby);
+  send_reg(reg_standby);
 }
 
 static void
 set_reg_int_divider(struct db_xcvr2450_dummy *db){
   int reg_int_divider = ((
-    (db->common.d_frac_div & 0x03)<<16) |
-    (db->common.d_int_div<<4)           | 3);
-  send_reg(db, reg_int_divider);
+    (db->common->d_frac_div & 0x03)<<16) |
+    (db->common->d_int_div<<4)           | 3);
+  send_reg(reg_int_divider);
 }
 
 static void
 set_reg_frac_divider(struct db_xcvr2450_dummy *db){
-  int reg_frac_divider = ((db->common.d_frac_div & 0xfffc)<<2) | 4;
-  send_reg(db, reg_frac_divider);
+  int reg_frac_divider = ((db->common->d_frac_div & 0xfffc)<<2) | 4;
+  send_reg(reg_frac_divider);
 }
 
 static void
 set_reg_bandselpll(struct db_xcvr2450_dummy *db){
-  int reg_bandselpll = ((db->common.d_mimo<<17) |
+  int reg_bandselpll = ((db->common->d_mimo<<17) |
     (1<<16) |
     (1<<15) |
     (0<<11) | //this bit gets toggled
-    (db->common.d_highband<<10)  |
-    (db->common.d_cp_current<<9) |
-    (db->common.d_ref_div<<5)    |
-    (db->common.d_five_gig<<4)   | 5);
-  send_reg(db, reg_bandselpll);
-  reg_bandselpll = ((db->common.d_mimo<<17) |
+    (db->common->d_highband<<10)  |
+    (db->common->d_cp_current<<9) |
+    (db->common->d_ref_div<<5)    |
+    (db->common->d_five_gig<<4)   | 5);
+  send_reg(reg_bandselpll);
+  reg_bandselpll = ((db->common->d_mimo<<17) |
     (1<<16) |
     (1<<15) |
     (1<<11) |
-    (db->common.d_highband<<10)  |
-    (db->common.d_cp_current<<9) |
-    (db->common.d_ref_div<<5)    |
-    (db->common.d_five_gig<<4)   | 5);
-  send_reg(db, reg_bandselpll);
+    (db->common->d_highband<<10)  |
+    (db->common->d_cp_current<<9) |
+    (db->common->d_ref_div<<5)    |
+    (db->common->d_five_gig<<4)   | 5);
+  send_reg(reg_bandselpll);
 }
 
 static void
@@ -198,64 +241,64 @@ set_reg_cal(struct db_xcvr2450_dummy *db){
   // FIXME do calibration
   int reg_cal = (
     (1<<14) | 6);
-  send_reg(db, reg_cal);
+  send_reg(reg_cal);
 }
 
 static void
 set_reg_lpf(struct db_xcvr2450_dummy *db){
   int reg_lpf = (
-    (db->common.d_rssi_hbw<<15)  |
-    (db->common.d_txlpf_bw<<10)  |
-    (db->common.d_rxlpf_bw<<9)   |
-    (db->common.d_rxlpf_fine<<4) | 7);
-  send_reg(db, reg_lpf);
+    (db->common->d_rssi_hbw<<15)  |
+    (db->common->d_txlpf_bw<<10)  |
+    (db->common->d_rxlpf_bw<<9)   |
+    (db->common->d_rxlpf_fine<<4) | 7);
+  send_reg(reg_lpf);
 }
 
 static void
 set_reg_rxrssi_ctrl(struct db_xcvr2450_dummy *db){
   int reg_rxrssi_ctrl = (
-       (db->common.d_rxvga_ser<<16)  |
-       (db->common.d_rssi_range<<15) |
-       (db->common.d_rssi_mode<<14)  |
-       (db->common.d_rssi_mux<<12)   |
+       (db->common->d_rxvga_ser<<16)  |
+       (db->common->d_rssi_range<<15) |
+       (db->common->d_rssi_mode<<14)  |
+       (db->common->d_rssi_mux<<12)   |
        (1<<9)                        |
-       (db->common.d_rx_hpf<<6)      |
+       (db->common->d_rx_hpf<<6)      |
        (1<<4)                        | 8);
-  send_reg(db, reg_rxrssi_ctrl);
+  send_reg(reg_rxrssi_ctrl);
 }
 
 static void
 set_reg_txlin_gain(struct db_xcvr2450_dummy *db){
   int reg_txlin_gain = (
-      (db->common.d_txvga_ser<<14)     |
-      (db->common.d_tx_driver_lin<<12) |
-      (db->common.d_tx_vga_lin<<10)    |
-      (db->common.d_tx_upconv_lin<<6)  |
-      (db->common.d_tx_bb_gain<<4)     | 9);
-  send_reg(db, reg_txlin_gain);
+      (db->common->d_txvga_ser<<14)     |
+      (db->common->d_tx_driver_lin<<12) |
+      (db->common->d_tx_vga_lin<<10)    |
+      (db->common->d_tx_upconv_lin<<6)  |
+      (db->common->d_tx_bb_gain<<4)     | 9);
+  send_reg(reg_txlin_gain);
 }
 
 static void
 set_reg_pabias(struct db_xcvr2450_dummy *db){
   int reg_pabias = (
-      (db->common.d_pabias_delay<<10) |
-      (db->common.d_pabias<<4)        | 10);
-  send_reg(db, reg_pabias);
+      (db->common->d_pabias_delay<<10) |
+      (db->common->d_pabias<<4)        | 10);
+  send_reg(reg_pabias);
 }
 
 static void
 set_reg_rxgain(struct db_xcvr2450_dummy *db){
   int reg_rxgain = (
-    (db->common.d_rx_rf_gain<<9) |
-    (db->common.d_rx_bb_gain<<4) | 11);
-  send_reg(db, reg_rxgain);
+    (db->common->d_rx_rf_gain<<9) |
+    (db->common->d_rx_bb_gain<<4) | 11);
+  send_reg(reg_rxgain);
 }
 
 static void
 set_reg_txgain(struct db_xcvr2450_dummy *db){
   int reg_txgain = (
-    (db->common.d_txgain<<4) | 12);
-  send_reg(db, reg_txgain);
+    (db->common->d_txgain<<4) | 12);
+  send_reg(reg_txgain);
 }
 
 /**************************************************
@@ -264,33 +307,12 @@ set_reg_txgain(struct db_xcvr2450_dummy *db){
 static void
 set_gpio(struct db_xcvr2450_dummy *db){
   //set tx/rx gpio pins for auto tr
-
-  int rx_hp, tx_antsel, rx_antsel, tx_pa_sel, ad9515_sel=0;
-
-  if(db->common.d_ad9515_div == 3)
-    ad9515_sel = AD9515DIV;
-  else if(db->common.d_ad9515_div == 2)
-    ad9515_sel = 0;
-
-  if(db->common.d_rx_hp_pin)
-    rx_hp = RX_HP;
-  else
-    rx_hp = 0;
-
-  if(db->common.d_tx_ant)
-    tx_antsel = ANTSEL_TX2_RX1;
-  else
-    tx_antsel = ANTSEL_TX1_RX2;
-
-  if(db->common.d_rx_ant)
-    rx_antsel = ANTSEL_TX2_RX1;
-  else
-    rx_antsel = ANTSEL_TX1_RX2;
-
-  if(db->common.d_five_gig)
-    tx_pa_sel = LB_PA_OFF;
-  else
-    tx_pa_sel = HB_PA_OFF;
+  int tx_enb_sel = (db->common->d_tx_enb)? TX_EN:0;
+  int ad9515_sel = (db->common->d_ad9515_div == 3)? AD9515DIV:0;
+  int rx_hp = (db->common->d_rx_hp_pin)? RX_HP:0;
+  int tx_antsel = (db->common->d_tx_ant)? ANTSEL_TX2_RX1:ANTSEL_TX1_RX2;
+  int rx_antsel = (db->common->d_rx_ant)? ANTSEL_TX2_RX1:ANTSEL_TX1_RX2;
+  int tx_pa_sel = (db->common->d_five_gig)? LB_PA_OFF:HB_PA_OFF;
 
   /* FIXME better way to set rx and tx val for RX and TX banks */
   /* set rx bank */
@@ -299,7 +321,7 @@ set_gpio(struct db_xcvr2450_dummy *db){
   set_atr_regs(GPIO_RX_BANK, (struct db_base *)db);
   /* set tx bank */
   db->base.atr_rxval = HB_PA_OFF|LB_PA_OFF|rx_antsel|ad9515_sel;
-  db->base.atr_txval = tx_pa_sel|tx_antsel|TX_EN|ad9515_sel;
+  db->base.atr_txval = tx_pa_sel|tx_antsel|tx_enb_sel|ad9515_sel;
   set_atr_regs(GPIO_TX_BANK, (struct db_base *)db);
 }
 
@@ -309,39 +331,8 @@ set_gpio(struct db_xcvr2450_dummy *db){
 bool
 xcvr2450_init(struct db_base *dbb){
   struct db_xcvr2450_dummy *db = (struct db_xcvr2450_dummy *) dbb;
-  /* set sane defaults */
-  db->common.d_mimo = 1;          // 0 = OFF, 1 = ON
-  db->common.d_int_div = 192;     // 128 = min, 255 = max
-  db->common.d_frac_div = 0;      // 0 = min, 65535 = max
-  db->common.d_highband = 0;      // 0 = freq <= 5.4e9, 1 = freq > 5.4e9
-  db->common.d_five_gig = 0;      // 0 = freq <= 3.e9, 1 = freq > 3e9
-  db->common.d_cp_current = 0;    // 0 = 2mA, 1 = 4mA
-  db->common.d_ref_div = 1;       // 1 to 7
-  db->common.d_rssi_hbw = 0;      // 0 = 2 MHz, 1 = 6 MHz
-  db->common.d_txlpf_bw = 1;      // 1 = 12 MHz, 2 = 18 MHz, 3 = 24 MHz
-  db->common.d_rxlpf_bw = 1;      // 0 = 7.5 MHz, 1 = 9.5 MHz, 2 = 14 MHz, 3 = 18 MHz
-  db->common.d_rxlpf_fine = 2;    // 0 = 90%, 1 = 95%, 2 = 100%, 3 = 105%, 4 = 110%
-  db->common.d_rxvga_ser = 1;     // 0 = RXVGA controlled by B7:1, 1=controlled serially
-  db->common.d_rssi_range = 1;    // 0 = low range (datasheet typo), 1=high range (0.5V - 2.0V)
-  db->common.d_rssi_mode = 1;     // 0 = enable follows RXHP, 1 = enabled
-  db->common.d_rssi_mux = 0;      // 0 = RSSI, 1 = TEMP
-  db->common.d_rx_hp_pin = 0;     // 0 = Fc set by rx_hpf, 1 = 600 KHz
-  db->common.d_rx_hpf = 0;        // 0 = 100Hz, 1 = 30KHz
-  db->common.d_rx_ant = 0;        // 0 = Ant. #1, 1 = Ant. #2
-  db->common.d_tx_ant = 0;        // 0 = Ant. #1, 1 = Ant. #2
-  db->common.d_txvga_ser = 1;     // 0 = TXVGA controlled by B6:1, 1=controlled serially
-  db->common.d_tx_driver_lin = 2; // 0=50% (worst linearity), 1=63%, 2=78%, 3=100% (best lin)
-  db->common.d_tx_vga_lin = 2;    // 0=50% (worst linearity), 1=63%, 2=78%, 3=100% (best lin)
-  db->common.d_tx_upconv_lin = 2; // 0=50% (worst linearity), 1=63%, 2=78%, 3=100% (best lin)
-  db->common.d_tx_bb_gain = 3;    // 0=maxgain-5dB, 1=max-3dB, 2=max-1.5dB, 3=max
-  db->common.d_pabias_delay = 15; // 0 = 0, 15 = 7uS
-  db->common.d_pabias = 0;        // 0 = 0 uA, 63 = 315uA
-  db->common.d_rx_rf_gain = 0;    // 0 = 0dB, 1 = 0dB, 2 = 15dB, 3 = 30dB
-  db->common.d_rx_bb_gain = 16;   // 0 = min, 31 = max (0 - 62 dB)
-  db->common.d_txgain = 63;       // 0 = min, 63 = max
-  db->common.spi_mask = SPI_SS_RX_DB;
   /* Initialize chipset */
-  clocks_enable_tx_dboard(true, REF_CLK_DIV);
+  clocks_enable_tx_dboard(true, MASTER_REF_CLK_DIV);
   set_gpio(db);
   set_reg_standby(db);
   set_reg_bandselpll(db);
@@ -382,59 +373,54 @@ bool
 xcvr2450_set_freq(struct db_base *dbb, u2_fxpt_freq_t freq, u2_fxpt_freq_t *dc){
   unsigned int scaler, div_factor, actual_div_q16;
   struct db_xcvr2450_dummy *db = (struct db_xcvr2450_dummy *) dbb;
-  /* ensure freq is within low range or high range */
-  if(!(
-    (freq >= db->base.freq_min && freq <= U2_DOUBLE_TO_FXPT_FREQ(2.6e9)) ||
-    (freq >= U2_DOUBLE_TO_FXPT_FREQ(4.8e9) && freq <= db->base.freq_max))) {
+  /* determine if the freq range is in low or high band */
+  if (freq >= LB_FREQ_MIN && freq <= LB_FREQ_MAX) {
+    db->common->d_five_gig = 0;
+    scaler = 3;
+    //printf("2.4-GHZ\n");
+  } else if (freq >= HB_FREQ_MIN && freq <= HB_FREQ_MAX) {
+    db->common->d_five_gig = 1;
+    scaler = 5;
+    //printf("5-GHZ\n");
+  } else {
+    printf("Out of range\n");
     return false;
   }
   /* set the highband bit */
   if(freq > U2_DOUBLE_TO_FXPT_FREQ(5.408e9)) {
-    db->common.d_highband = 1;
+    db->common->d_highband = 1;
     //printf("5-HB\n");
   }
   else {
-    db->common.d_highband = 0;
+    db->common->d_highband = 0;
     //printf("5-LB\n");
   }
-  /* set the 5 gig bit, determine scaler */
-  if(freq > U2_DOUBLE_TO_FXPT_FREQ(4e9)) {
-    db->common.d_five_gig = 1;
-    scaler = 5;
-    //printf("5-GHZ\n");
-  } else {
-    db->common.d_five_gig = 0;
-    scaler = 3;
-    //printf("2.4-GHZ\n");
-  }
-  /* set the dividers so that div_int >= 131, practical minimum */
-  db->common.d_int_div = 0;
   unsigned int loop_iter = 0;
-  while (db->common.d_int_div < 131){
+  do { /* set the dividers so that the n divider is above the practical minimum */
     switch(loop_iter){
       case 0:
-        db->common.d_ad9515_div = 3;
-        db->common.d_ref_div = 1;
+        db->common->d_ad9515_div = 3;
+        db->common->d_ref_div = 1;
         break;
       case 1:
-        db->common.d_ad9515_div = 2;
-        db->common.d_ref_div = 2;
+        db->common->d_ad9515_div = 2;
+        db->common->d_ref_div = 2;
         break;
       default:
-        db->common.d_ad9515_div = 3;
-        db->common.d_ref_div = loop_iter;
+        db->common->d_ad9515_div = 3;
+        db->common->d_ref_div = loop_iter;
     }
     loop_iter++;
-    div_factor = db->common.d_ref_div*db->common.d_ad9515_div*4*REF_CLK_DIV;
-    /* calculate the fractional divisor */
+    div_factor = db->common->d_ref_div*db->common->d_ad9515_div*4*MASTER_REF_CLK_DIV;
     actual_div_q16 = ((freq*div_factor)/(scaler*MASTER_CLK_RATE)) >> (U2_FPF_RP-16);
-    db->common.d_int_div = actual_div_q16 >> 16;
-  }
-  db->common.d_frac_div = actual_div_q16 & 0xffff; //isolate lower 16 bits
+  } while (actual_div_q16 < N_DIV_MIN_Q16);
+  /* calculate the divisors */
+  db->common->d_int_div = actual_div_q16 >> 16;
+  db->common->d_frac_div = actual_div_q16 & 0xffff; //isolate lower 16 bits
   /* calculate the dc freq */
   *dc = ((((u2_fxpt_freq_t)MASTER_CLK_RATE)*actual_div_q16*scaler) / div_factor) << (U2_FPF_RP-16);
   /*printf("scaler %d, div(int) %u, div_factor %d, ad9515_div %u, ref_div %u\n",
-    scaler, db->common.d_int_div, div_factor, db->common.d_ad9515_div, db->common.d_ref_div);
+    scaler, db->common->d_int_div, div_factor, db->common->d_ad9515_div, db->common->d_ref_div);
   printf("actual div %u, Target Freq %uKHz, Actual Freq %uKHz\n",
     actual_div_q16, u2_fxpt_freq_round_to_int(freq/1000), u2_fxpt_freq_round_to_int(*dc/1000));
   */
@@ -463,18 +449,18 @@ xcvr2450_set_gain_rx(struct db_base *dbb, u2_fxpt_gain_t gain){
   // Split the gain between RF and baseband
   // This is experimental, not prescribed
   if(gain < U2_DOUBLE_TO_FXPT_GAIN(30.0)) {
-    db->common.d_rx_rf_gain = 0; // 0 dB RF gain
-    db->common.d_rx_bb_gain = u2_fxpt_gain_round_to_int(gain/2);
+    db->common->d_rx_rf_gain = 0; // 0 dB RF gain
+    db->common->d_rx_bb_gain = u2_fxpt_gain_round_to_int(gain/2);
   }
   else if(gain >= U2_DOUBLE_TO_FXPT_GAIN(30.0) && gain < U2_DOUBLE_TO_FXPT_GAIN(61.0)) {
-    db->common.d_rx_rf_gain = 2; // 15 dB RF gain
-    db->common.d_rx_bb_gain = u2_fxpt_gain_round_to_int((gain-U2_DOUBLE_TO_FXPT_GAIN(15.0))/2);
+    db->common->d_rx_rf_gain = 2; // 15 dB RF gain
+    db->common->d_rx_bb_gain = u2_fxpt_gain_round_to_int((gain-U2_DOUBLE_TO_FXPT_GAIN(15.0))/2);
   }
   else if(gain >= U2_DOUBLE_TO_FXPT_GAIN(61.0)) {
-    db->common.d_rx_rf_gain = 3; // 30.5 dB RF gain
-    db->common.d_rx_bb_gain = u2_fxpt_gain_round_to_int((gain-U2_DOUBLE_TO_FXPT_GAIN(30.5))/2);
+    db->common->d_rx_rf_gain = 3; // 30.5 dB RF gain
+    db->common->d_rx_bb_gain = u2_fxpt_gain_round_to_int((gain-U2_DOUBLE_TO_FXPT_GAIN(30.5))/2);
   }
-  //printf("RX RF Gain %u, RX BB Gain %u\n", db->common.d_rx_rf_gain, db->common.d_rx_bb_gain);
+  //printf("RX RF Gain %u, RX BB Gain %u\n", db->common->d_rx_rf_gain, db->common->d_rx_bb_gain);
   set_reg_rxgain(db);
   return true;
 }
@@ -490,8 +476,18 @@ xcvr2450_set_gain_tx(struct db_base *dbb, u2_fxpt_gain_t gain){
     return false;
   }
   //scale for register and set
-  db->common.d_txgain = gain/db->base.gain_step_size;
-  //printf("TX Gain %u\n", db->common.d_txgain);
+  db->common->d_txgain = (gain*63)/db->base.gain_max;
+  //printf("TX Gain %u, TX Reg %u\n", u2_fxpt_gain_round_to_int(gain), db->common->d_txgain);
   set_reg_txgain(db);
   return true;
 }
+
+/**************************************************
+ * Set TX Enable
+ **************************************************/
+bool
+xcvr2450_set_tx_enable(struct db_base *dbb, bool on){
+  struct db_xcvr2450_dummy *db = (struct db_xcvr2450_dummy *) dbb;
+  db->common->d_tx_enb = on;
+  return true;
+}