Merge branch 'new_eth' of http://gnuradio.org/git/matt into master

* 'new_eth' of http://gnuradio.org/git/matt: (42 commits)
  Fix warnings, mostly from implicitly defined wires or unspecified widths
  fullchip sim now compiles again, after moving eth and models over to new simple_gemac
  remove unused opencores
  remove debugging code
  no idea where this came from, it shouldn't be here
  Copied wb_1master back from quad radio
  Remove old mac.  Good riddance.
  remove unused port
  More xilinx fifos, more clean up of our fifos
  might as well use a cascade fifo to help timing and give a little more capacity
  fix a typo which caused tx glitches
  Untested fixes for getting serdes onto the new fifo system.  Compiles, at least
  Implement Eth flow control using pause frames
  parameterized fifo sizes, some reformatting
  remove unused old style fifo
  allow control of whether or not to honor flow control, adds some debug lines
  debug the rx side
  no longer used, replaced by newfifo version
  remove special last_line adjustment from ethernet port
  Firmware now inserts mac source address value in each frame.
  ...

5 files changed, 65 insertions, 100 deletions

diff --git a/usrp2/firmware/lib/.gitignore b/usrp2/firmware/lib/.gitignore
index f1cc2bf73..5d838bf6c 100644
--- a/usrp2/firmware/lib/.gitignore
+++ b/usrp2/firmware/lib/.gitignore
@@ -1,3 +1,4 @@
+*~
 /*-stamp
 /*.a
 /*.bin
diff --git a/usrp2/firmware/lib/dbsm.c b/usrp2/firmware/lib/dbsm.c
index 8f774d916..96484d577 100644
--- a/usrp2/firmware/lib/dbsm.c
+++ b/usrp2/firmware/lib/dbsm.c
@@ -62,7 +62,8 @@ dbsm_init(dbsm_t *sm, int buf0,
 
   // How much to adjust the last_line register.
   // It's 1 for everything but the ethernet.
-  sm->last_line_adj = recv->port == PORT_ETH ? 3 : 1;
+  //sm->last_line_adj = recv->port == PORT_ETH ? 3 : 1;
+  sm->last_line_adj = 1;
 
   buffer_state[sm->buf0] = BS_EMPTY;
   buffer_state[sm->buf0 ^ 1] = BS_EMPTY;
diff --git a/usrp2/firmware/lib/eth_mac.c b/usrp2/firmware/lib/eth_mac.c
index 5fadaf40b..88051dca0 100644
--- a/usrp2/firmware/lib/eth_mac.c
+++ b/usrp2/firmware/lib/eth_mac.c
@@ -21,38 +21,21 @@
 #include "bool.h"
 #include "eth_phy.h"	// for simulation constants
 #include "mdelay.h"
-
+#include "stdio.h"
 
 #define PHY_ADDR 1
 
 void
 eth_mac_set_addr(const u2_mac_addr_t *src)
 {
-  int i;
-
-  // tell mac our source address and enable automatic insertion on Tx.
-  eth_mac->mac_tx_add_prom_wr = 0;	// just in case
-  for (i = 0; i < 6; i++){
-    eth_mac->mac_tx_add_prom_add = i;
-    eth_mac->mac_tx_add_prom_data = src->addr[i];
-    eth_mac->mac_tx_add_prom_wr = 1;
-    mdelay(1);
-    eth_mac->mac_tx_add_prom_wr = 0;
-    mdelay(1);
-  }
-  eth_mac->mac_tx_add_en = 1;  // overwrite pkt src addr field with this stuff
-
-  // set up receive destination address filter
-  eth_mac->mac_rx_add_prom_wr = 0;	// just in case
-  for (i = 0; i < 6; i++){
-    eth_mac->mac_rx_add_prom_add = i;
-    eth_mac->mac_rx_add_prom_data = src->addr[i];
-    eth_mac->mac_rx_add_prom_wr = 1;
-    mdelay(1);
-    eth_mac->mac_rx_add_prom_wr = 0;
-    mdelay(1);
-  }
-  // eth_mac->mac_rx_add_chk_en = 1;  // FIXME enable when everything's working
+  eth_mac->ucast_hi = 
+    (((unsigned int)src->addr[0])<<8) + 
+    ((unsigned int)src->addr[1]);
+  eth_mac->ucast_lo = 
+    (((unsigned int)src->addr[2])<<24) + 
+    (((unsigned int)src->addr[3])<<16) +
+    (((unsigned int)src->addr[4])<<8) +
+    (((unsigned int)src->addr[5]));
 }
 
 
@@ -62,14 +45,18 @@ eth_mac_init(const u2_mac_addr_t *src)
   eth_mac->miimoder = 25;	// divider from CPU clock (50MHz/25 = 2MHz)
 
   eth_mac_set_addr(src);
+  eth_mac->settings = MAC_SET_PAUSE_EN | MAC_SET_PASS_BCAST | MAC_SET_PASS_UCAST | MAC_SET_PAUSE_SEND_EN; 
+
+  eth_mac->pause_time = 38;
+  eth_mac->pause_thresh = 1200;
 
   // set rx flow control high and low water marks
   // unsigned int lwmark = (2*2048 + 64)/4; // 2 * 2048-byte frames + 1 * 64-byte pause frame
   // eth_mac->fc_hwmark = lwmark + 2048/4;  // plus a 2048-byte frame
 
-  eth_mac->fc_lwmark = 600;		// there are currently 2047 lines in the fifo
-  eth_mac->fc_hwmark = 1200;
-  eth_mac->fc_padtime = 1700;           // how long before flow control runs out do we 
+  //  eth_mac->fc_lwmark = 600;		// there are currently 2047 lines in the fifo
+  // eth_mac->fc_hwmark = 1200;
+  //eth_mac->fc_padtime = 1700;           // how long before flow control runs out do we 
                                         // request a re-pause.  Units of 8ns (bytes)
 
   //eth_mac->tx_pause_en = 0;		// pay attn to pause frames sent to us
@@ -80,8 +67,8 @@ eth_mac_init(const u2_mac_addr_t *src)
 int
 eth_mac_read_rmon(int addr)
 {
-  int t;
-  
+  int t = 0;
+  /*  
   eth_mac->rmon_rd_addr = addr;
   eth_mac->rmon_rd_apply = 1;
   while(eth_mac->rmon_rd_grant == 0)
@@ -89,6 +76,7 @@ eth_mac_read_rmon(int addr)
 
   t = eth_mac->rmon_rd_dout;
   eth_mac->rmon_rd_apply = 0;
+  */
   return t;
 }
 
@@ -111,7 +99,9 @@ eth_mac_miim_read(int addr)
   while((eth_mac->miistatus & MIIS_BUSY) != 0)
     ;
 
-  return eth_mac->miirx_data;
+  int r = eth_mac->miirx_data;
+  //printf("MIIM-READ ADDR 0x%x DATA 0x%x\n",addr, r);
+  return r;
 }
 
 void
@@ -122,6 +112,7 @@ eth_mac_miim_write(int addr, int value)
   eth_mac->miitx_data = value;
   eth_mac->miicommand = MIIC_WCTRLDATA;
 
+  //printf("MIIM-WRITE ADDR 0x%x VAL 0x%x\n",addr,value);
   while((eth_mac->miistatus & MIIS_BUSY) != 0)
     ;
 }
diff --git a/usrp2/firmware/lib/eth_mac_regs.h b/usrp2/firmware/lib/eth_mac_regs.h
index 8daab937d..d680f8de0 100644
--- a/usrp2/firmware/lib/eth_mac_regs.h
+++ b/usrp2/firmware/lib/eth_mac_regs.h
@@ -20,70 +20,34 @@
 #define INCLUDED_ETH_MAC_REGS_H
 
 /*
- * See opencores.org 10_100_1000 Mbps Tri-mode Ethernet MAC Specification
+ * Simple GEMAC
  *
- * In reality, these are 16-bit regs, but are assigned
- * on 32-bit boundaries.  Because we're little endian,
- * declaring them "int" works.
  */
 typedef struct {
-  volatile int	tx_hwmark;
-  volatile int	tx_lwmark;
-
-  //! if set, send pause frames automatically
-  volatile int	pause_frame_send_en;
-
-  //! quanta value for pause frame in units of 512 bit times.
-  volatile int	pause_quanta_set;
-
-  volatile int	ifg_set;
-  volatile int	full_duplex;
-  volatile int	max_retry;
-  volatile int	mac_tx_add_en;
-  volatile int	mac_tx_add_prom_data;
-  volatile int	mac_tx_add_prom_add;
-  volatile int	mac_tx_add_prom_wr;
-
-  //! if set, other end can pause us (i.e., we pay attention to pause frames)
-  volatile int	tx_pause_en;
-
-  // Flow Control high and low water marks
-  //! when space available (in 32-bit lines) > hwmark, send un-pause frame
-  volatile int	fc_hwmark;	
-
-  //! when space avail (in 32-bit lines) < lwmark, send pause frame
-  volatile int	fc_lwmark;	
-
-  volatile int	mac_rx_add_chk_en;
-  volatile int	mac_rx_add_prom_data;
-  volatile int	mac_rx_add_prom_add;
-  volatile int	mac_rx_add_prom_wr;
-  volatile int	broadcast_filter_en;
-  volatile int	broadcast_bucket_depth;
-  volatile int	broadcast_bucket_interval;
-  volatile int	rx_append_crc;
-  volatile int	rx_hwmark;
-  volatile int	rx_lwmark;
-  volatile int	crc_chk_en;
-  volatile int	rx_ifg_set;
-  volatile int	rx_max_length;
-  volatile int	rx_min_length;
-  volatile int	rmon_rd_addr;		// performance counter access
-  volatile int	rmon_rd_apply;		
-  volatile int	rmon_rd_grant;		// READONLY
-  volatile int	rmon_rd_dout;	        // READONLY
-  volatile int	dummy;	// READONLY
-  volatile int	line_loop_en;
-  volatile int	speed;
-  volatile int	miimoder;
-  volatile int	miicommand;
-  volatile int	miiaddress;
-  volatile int	miitx_data;
-  volatile int	miirx_data;
-  volatile int	miistatus;
-  volatile int	fc_padtime;
+  volatile int settings;
+  volatile int ucast_hi;
+  volatile int ucast_lo;
+  volatile int mcast_hi;
+  volatile int mcast_lo;
+  volatile int miimoder;
+  volatile int miiaddress;
+  volatile int miitx_data;
+  volatile int miicommand;
+  volatile int miistatus;
+  volatile int miirx_data;
+  volatile int pause_time;
+  volatile int pause_thresh;
 } eth_mac_regs_t;
 
+// settings register
+#define MAC_SET_PAUSE_EN  (1 << 0)   // Makes us respect received pause frames (normally on)
+#define MAC_SET_PASS_ALL  (1 << 1)   // Enables promiscuous mode, currently broken
+#define MAC_SET_PASS_PAUSE (1 << 2)  // Sends pause frames through (normally off)
+#define MAC_SET_PASS_BCAST (1 << 3)  // Sends broadcast frames through (normally on)
+#define MAC_SET_PASS_MCAST (1 << 4)  // Sends multicast frames that match mcast addr (normally off)
+#define MAC_SET_PASS_UCAST (1 << 5)  // Sends unicast (normal) frames through if they hit in address filter (normally on)
+#define MAC_SET_PAUSE_SEND_EN (1 << 6) // Enables sending pause frames
+
 // miicommand register
 #define MIIC_SCANSSTAT	(1 << 0)	// Scan status
 #define MIIC_RSTAT      (1 << 1)	// Read status
diff --git a/usrp2/firmware/lib/ethernet.c b/usrp2/firmware/lib/ethernet.c
index d19287044..f554e0179 100644
--- a/usrp2/firmware/lib/ethernet.c
+++ b/usrp2/firmware/lib/ethernet.c
@@ -43,6 +43,8 @@ ethernet_register_link_changed_callback(ethernet_link_changed_callback_t new_cal
 static void
 ed_set_mac_speed(int speed)
 {
+  printf("Speed set to %d\n",speed);
+  /*
   switch(speed){
   case 10:
     eth_mac->speed = 1;
@@ -56,6 +58,7 @@ ed_set_mac_speed(int speed)
   default:
     break;
   }
+  */
 }
 
 static void
@@ -196,17 +199,17 @@ ethernet_init(void)
   ed_state.link_speed = S_UNKNOWN;
 
   // initialize MAC registers
-  eth_mac->tx_hwmark = 0x1e;
-  eth_mac->tx_lwmark = 0x19;
+  //  eth_mac->tx_hwmark = 0x1e;
+  //eth_mac->tx_lwmark = 0x19;
 
-  eth_mac->crc_chk_en = 1;
-  eth_mac->rx_max_length = 2048;
+  //eth_mac->crc_chk_en = 1;
+  //eth_mac->rx_max_length = 2048;
 
   // configure PAUSE frame stuff
-  eth_mac->tx_pause_en = 1;		// pay attn to pause frames sent to us
+  //eth_mac->tx_pause_en = 1;		// pay attn to pause frames sent to us
 
-  eth_mac->pause_quanta_set = 38;	// a bit more than 1 max frame 16kb/512 + fudge
-  eth_mac->pause_frame_send_en = 1;	// enable sending pause frames
+  //eth_mac->pause_quanta_set = 38;	// a bit more than 1 max frame 16kb/512 + fudge
+  //eth_mac->pause_frame_send_en = 1;	// enable sending pause frames
 
 
   // setup PHY to interrupt on changes
@@ -256,6 +259,10 @@ ethernet_init(void)
   t &= ~(NWAY_AR_10T_HD_CAPS | NWAY_AR_10T_FD_CAPS | NWAY_AR_100TX_HD_CAPS | NWAY_AR_100TX_FD_CAPS);
 
   eth_mac_miim_write(PHY_AUTONEG_ADV, t);
+  int r = eth_mac_miim_read(PHY_AUTONEG_ADV);  		// DEBUG, read back
+  if (t != r){
+    printf("PHY_AUTONEG_ADV: wrote 0x%x, got 0x%x\n", t, r);
+  }
 
   // Restart autonegotation.  
   // We want to ensure that we're advertising our PAUSE capabilities.
@@ -322,6 +329,7 @@ ethernet_check_errors(void)
   // these registers are reset when read
   
   int	r = 0;
+  /*
   if (eth_mac_read_rmon(0x05) != 0)
     r |= RME_RX_CRC;
   if (eth_mac_read_rmon(0x06) != 0)
@@ -335,6 +343,6 @@ ethernet_check_errors(void)
     r |= RME_TX_FIFO_UNDER;
   if (eth_mac_read_rmon(0x27) != 0)
     r |= RME_TX_FIFO_OVER;
-
+  */
   return r;
 }