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| author | eb | 2007-03-05 05:00:02 +0000 |
|---|---|---|
| committer | eb | 2007-03-05 05:00:02 +0000 |
| commit | c458230f2adc497dc1cb291934e75fe5a97a4450 (patch) | |
| tree | 8e677aa80ee3ddbc2198cedba08e7e33a612c413 /usrp/fpga/toplevel/usrp_std/usrp_std.qsf | |
| parent | e92d03cf19be0c915e7b8fd3d87a9bf1f547efc9 (diff) | |
| download | gnuradio-c458230f2adc497dc1cb291934e75fe5a97a4450.tar.gz gnuradio-c458230f2adc497dc1cb291934e75fe5a97a4450.tar.bz2 gnuradio-c458230f2adc497dc1cb291934e75fe5a97a4450.zip | |
Refactored FPGA *.vh files. Moved common pieces to toplevel/include.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4713 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'usrp/fpga/toplevel/usrp_std/usrp_std.qsf')
| -rw-r--r-- | usrp/fpga/toplevel/usrp_std/usrp_std.qsf | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/usrp/fpga/toplevel/usrp_std/usrp_std.qsf b/usrp/fpga/toplevel/usrp_std/usrp_std.qsf index fe6773f67..e43d39ba3 100644 --- a/usrp/fpga/toplevel/usrp_std/usrp_std.qsf +++ b/usrp/fpga/toplevel/usrp_std/usrp_std.qsf @@ -370,7 +370,6 @@ set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v -set_global_assignment -name VERILOG_FILE usrp_std.vh set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/acc.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mult.v |