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| author | jcorgan | 2007-11-01 03:29:36 +0000 |
|---|---|---|
| committer | jcorgan | 2007-11-01 03:29:36 +0000 |
| commit | a5f7fe576829f66d1a33ab339f406a9c3b18cf72 (patch) | |
| tree | 49b1866a6a6da70966a339c685ebf6efe100f361 /usrp/fpga/toplevel/usrp_std/usrp_std.qsf | |
| parent | cdc4b7416c50dd46c666220e01ff1bd6101085ab (diff) | |
| download | gnuradio-a5f7fe576829f66d1a33ab339f406a9c3b18cf72.tar.gz gnuradio-a5f7fe576829f66d1a33ab339f406a9c3b18cf72.tar.bz2 gnuradio-a5f7fe576829f66d1a33ab339f406a9c3b18cf72.zip | |
Merged r6749:6763 from jcorgan/t179. Fixes ticket:179. New RBFs synthesized with 7.1SP1.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@6764 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'usrp/fpga/toplevel/usrp_std/usrp_std.qsf')
| -rw-r--r-- | usrp/fpga/toplevel/usrp_std/usrp_std.qsf | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp/fpga/toplevel/usrp_std/usrp_std.qsf b/usrp/fpga/toplevel/usrp_std/usrp_std.qsf index 269d3c8f8..e0bac4893 100644 --- a/usrp/fpga/toplevel/usrp_std/usrp_std.qsf +++ b/usrp/fpga/toplevel/usrp_std/usrp_std.qsf @@ -370,6 +370,7 @@ set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k_18.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/atr_delay.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_dec_shifter.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v @@ -381,7 +382,6 @@ set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/ram16_2sum.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_rom.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/halfband_decim.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mac.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_ram.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_chain.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_dcoffset.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/adc_interface.v |