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authorJohnathan Corgan2010-02-28 12:47:43 -0800
committerJohnathan Corgan2010-02-28 12:47:43 -0800
commita2c00f5cff7407ff10fc6c812d06fefe52c0b6a3 (patch)
tree77121ca27b951f9bd687dbba33f6a9383ac74d5a /usrp/fpga/toplevel/sizetest/sizetest.ssf
parentdb29a2cfc18554ae0a3c55a4e13dc4cbfa86317f (diff)
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Remove usrp1 and usrp2 FPGA files. These are now hosted at:
git://ettus.sourcerepo.com/ettus/fpga.git ...under the 'usrp1' and 'usrp2' top-level directories.
Diffstat (limited to 'usrp/fpga/toplevel/sizetest/sizetest.ssf')
-rw-r--r--usrp/fpga/toplevel/sizetest/sizetest.ssf14
1 files changed, 0 insertions, 14 deletions
diff --git a/usrp/fpga/toplevel/sizetest/sizetest.ssf b/usrp/fpga/toplevel/sizetest/sizetest.ssf
deleted file mode 100644
index 1aceab1f1..000000000
--- a/usrp/fpga/toplevel/sizetest/sizetest.ssf
+++ /dev/null
@@ -1,14 +0,0 @@
-SIMULATOR_SETTINGS
-{
- ESTIMATE_POWER_CONSUMPTION = OFF;
- GLITCH_INTERVAL = 1NS;
- GLITCH_DETECTION = OFF;
- SIMULATION_COVERAGE = ON;
- CHECK_OUTPUTS = OFF;
- SETUP_HOLD_DETECTION = OFF;
- POWER_ESTIMATION_START_TIME = "0 NS";
- ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS = ON;
- SIMULATION_MODE = TIMING;
- START_TIME = 0NS;
- USE_COMPILER_SETTINGS = sizetest;
-}