summaryrefslogtreecommitdiff
path: root/usrp/fpga/sdr_lib/sign_extend.v
diff options
context:
space:
mode:
authorjcorgan2006-08-03 04:51:51 +0000
committerjcorgan2006-08-03 04:51:51 +0000
commit5d69a524f81f234b3fbc41d49ba18d6f6886baba (patch)
treeb71312bf7f1e8d10fef0f3ac6f28784065e73e72 /usrp/fpga/sdr_lib/sign_extend.v
downloadgnuradio-5d69a524f81f234b3fbc41d49ba18d6f6886baba.tar.gz
gnuradio-5d69a524f81f234b3fbc41d49ba18d6f6886baba.tar.bz2
gnuradio-5d69a524f81f234b3fbc41d49ba18d6f6886baba.zip
Houston, we have a trunk.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@3122 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'usrp/fpga/sdr_lib/sign_extend.v')
-rw-r--r--usrp/fpga/sdr_lib/sign_extend.v35
1 files changed, 35 insertions, 0 deletions
diff --git a/usrp/fpga/sdr_lib/sign_extend.v b/usrp/fpga/sdr_lib/sign_extend.v
new file mode 100644
index 000000000..2417909bd
--- /dev/null
+++ b/usrp/fpga/sdr_lib/sign_extend.v
@@ -0,0 +1,35 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+//
+
+
+// Sign extension "macro"
+// bits_out should be greater than bits_in
+
+module sign_extend (in,out);
+ parameter bits_in=0; // FIXME Quartus insists on a default
+ parameter bits_out=0;
+
+ input [bits_in-1:0] in;
+ output [bits_out-1:0] out;
+
+ assign out = {{(bits_out-bits_in){in[bits_in-1]}},in};
+
+endmodule