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authorjcorgan2006-08-03 04:51:51 +0000
committerjcorgan2006-08-03 04:51:51 +0000
commit5d69a524f81f234b3fbc41d49ba18d6f6886baba (patch)
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Diffstat (limited to 'usrp/fpga/sdr_lib/setting_reg_masked.v')
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diff --git a/usrp/fpga/sdr_lib/setting_reg_masked.v b/usrp/fpga/sdr_lib/setting_reg_masked.v
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+++ b/usrp/fpga/sdr_lib/setting_reg_masked.v
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+
+
+module setting_reg_masked
+ ( input clock, input reset, input strobe, input wire [6:0] addr,
+ input wire [31:0] in, output reg [31:0] out, output reg changed);
+/* upper 16 bits are mask, lower 16 bits are value
+ * Note that you get a 16 bit register, not a 32 bit one */
+
+ parameter my_addr = 0;
+
+ always @(posedge clock)
+ if(reset)
+ begin
+ out <= #1 32'd0;
+ changed <= #1 1'b0;
+ end
+ else
+ if(strobe & (my_addr==addr))
+ begin
+ out <= #1 (out & ~in[31:16]) | (in[15:0] & in[31:16] );
+ changed <= #1 1'b1;
+ end
+ else
+ changed <= #1 1'b0;
+
+endmodule // setting_reg_masked