Remove usrp1 and usrp2 FPGA files. These are now hosted at:

git://ettus.sourcerepo.com/ettus/fpga.git

...under the 'usrp1' and 'usrp2' top-level directories.

1 files changed, 0 insertions, 23 deletions

diff --git a/usrp/fpga/sdr_lib/setting_reg.v b/usrp/fpga/sdr_lib/setting_reg.v
deleted file mode 100644
index 3d31a9efb..000000000
--- a/usrp/fpga/sdr_lib/setting_reg.v
+++ /dev/null
@@ -1,23 +0,0 @@
-
-
-module setting_reg
-  ( input clock, input reset, input strobe, input wire [6:0] addr,
-    input wire [31:0] in, output reg [31:0] out, output reg changed);
-   parameter my_addr = 0;
-   
-   always @(posedge clock)
-     if(reset)
-       begin
-	  out <= #1 32'd0;
-	  changed <= #1 1'b0;
-       end
-     else
-       if(strobe & (my_addr==addr))
-	 begin
-	    out <= #1 in;
-	    changed <= #1 1'b1;
-	 end
-       else
-	 changed <= #1 1'b0;
-   
-endmodule // setting_reg