Remove usrp1 and usrp2 FPGA files. These are now hosted at:

git://ettus.sourcerepo.com/ettus/fpga.git

...under the 'usrp1' and 'usrp2' top-level directories.

1 files changed, 0 insertions, 17 deletions

diff --git a/usrp/fpga/sdr_lib/ram32.v b/usrp/fpga/sdr_lib/ram32.v
deleted file mode 100644
index 064e2735a..000000000
--- a/usrp/fpga/sdr_lib/ram32.v
+++ /dev/null
@@ -1,17 +0,0 @@
-
-
-module ram32 (input clock, input write, 
-	      input [4:0] wr_addr, input [15:0] wr_data,
-	      input [4:0] rd_addr, output reg [15:0] rd_data);
-
-   reg [15:0] 		ram_array [0:31];
-
-   always @(posedge clock)
-     rd_data <= #1 ram_array[rd_addr];
-
-   always @(posedge clock)
-     if(write)
-       ram_array[wr_addr] <= #1 wr_data;
-
-endmodule // ram32
-