Remove usrp1 and usrp2 FPGA files. These are now hosted at:

git://ettus.sourcerepo.com/ettus/fpga.git

...under the 'usrp1' and 'usrp2' top-level directories.

1 files changed, 0 insertions, 16 deletions

diff --git a/usrp/fpga/sdr_lib/hb/mult.v b/usrp/fpga/sdr_lib/hb/mult.v
deleted file mode 100644
index a8d4cb1b7..000000000
--- a/usrp/fpga/sdr_lib/hb/mult.v
+++ /dev/null
@@ -1,16 +0,0 @@
-
-
-module mult (input clock, input signed [15:0] x, input signed [15:0] y, output reg signed [30:0] product,
-	     input enable_in, output reg enable_out );
-
-   always @(posedge clock)
-     if(enable_in)
-       product <= #1 x*y;
-     else
-       product <= #1 31'd0;
-   
-   always @(posedge clock)
-     enable_out <= #1 enable_in;
-   
-endmodule // mult
-