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authorJohnathan Corgan2010-02-28 12:47:43 -0800
committerJohnathan Corgan2010-02-28 12:47:43 -0800
commita2c00f5cff7407ff10fc6c812d06fefe52c0b6a3 (patch)
tree77121ca27b951f9bd687dbba33f6a9383ac74d5a /usrp/fpga/sdr_lib/hb/coeff_rom.v
parentdb29a2cfc18554ae0a3c55a4e13dc4cbfa86317f (diff)
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Remove usrp1 and usrp2 FPGA files. These are now hosted at:
git://ettus.sourcerepo.com/ettus/fpga.git ...under the 'usrp1' and 'usrp2' top-level directories.
Diffstat (limited to 'usrp/fpga/sdr_lib/hb/coeff_rom.v')
-rw-r--r--usrp/fpga/sdr_lib/hb/coeff_rom.v19
1 files changed, 0 insertions, 19 deletions
diff --git a/usrp/fpga/sdr_lib/hb/coeff_rom.v b/usrp/fpga/sdr_lib/hb/coeff_rom.v
deleted file mode 100644
index 7f8886b4e..000000000
--- a/usrp/fpga/sdr_lib/hb/coeff_rom.v
+++ /dev/null
@@ -1,19 +0,0 @@
-
-
-module coeff_rom (input clock, input [2:0] addr, output reg [15:0] data);
-
- always @(posedge clock)
- case (addr)
- 3'd0 : data <= #1 -16'd49;
- 3'd1 : data <= #1 16'd165;
- 3'd2 : data <= #1 -16'd412;
- 3'd3 : data <= #1 16'd873;
- 3'd4 : data <= #1 -16'd1681;
- 3'd5 : data <= #1 16'd3135;
- 3'd6 : data <= #1 -16'd6282;
- 3'd7 : data <= #1 16'd20628;
- endcase // case(addr)
-
-endmodule // coeff_rom
-
-