Remove usrp1 and usrp2 FPGA files. These are now hosted at:

git://ettus.sourcerepo.com/ettus/fpga.git

...under the 'usrp1' and 'usrp2' top-level directories.

1 files changed, 0 insertions, 22 deletions

diff --git a/usrp/fpga/sdr_lib/hb/acc.v b/usrp/fpga/sdr_lib/hb/acc.v
deleted file mode 100644
index 195d5ea94..000000000
--- a/usrp/fpga/sdr_lib/hb/acc.v
+++ /dev/null
@@ -1,22 +0,0 @@
-
-
-module acc (input clock, input reset, input clear, input enable_in, output reg enable_out,
-	    input signed [30:0] addend, output reg signed [33:0] sum );
-
-   always @(posedge clock)
-     if(reset)
-       sum <= #1 34'd0;
-     //else if(clear & enable_in)
-     //  sum <= #1 addend;
-     //else if(clear)
-     //  sum <= #1 34'd0;
-     else if(clear)
-       sum <= #1 addend;
-     else if(enable_in)
-       sum <= #1 sum + addend;
-
-   always @(posedge clock)
-     enable_out <= #1 enable_in;
-   
-endmodule // acc
-