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author | jcorgan | 2006-08-03 04:51:51 +0000 |
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committer | jcorgan | 2006-08-03 04:51:51 +0000 |
commit | 5d69a524f81f234b3fbc41d49ba18d6f6886baba (patch) | |
tree | b71312bf7f1e8d10fef0f3ac6f28784065e73e72 /usrp/fpga/models/ssram.v | |
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Houston, we have a trunk.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@3122 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'usrp/fpga/models/ssram.v')
-rw-r--r-- | usrp/fpga/models/ssram.v | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/usrp/fpga/models/ssram.v b/usrp/fpga/models/ssram.v new file mode 100644 index 000000000..fd7339970 --- /dev/null +++ b/usrp/fpga/models/ssram.v @@ -0,0 +1,38 @@ + +// Model of Pipelined [ZBT] Synchronous SRAM + +module ssram(clock,addr,data,wen,ce); + parameter addrbits = 19; + parameter depth = 524288; + + input clock; + input [addrbits-1:0] addr; + inout [35:0] data; + input wen; + input ce; + + reg [35:0] ram [0:depth-1]; + + reg read_d1,read_d2; + reg write_d1,write_d2; + reg [addrbits-1:0] addr_d1,addr_d2; + + always @(posedge clock) + begin + read_d1 <= #1 ce & ~wen; + write_d1 <= #1 ce & wen; + addr_d1 <= #1 addr; + read_d2 <= #1 read_d1; + write_d2 <= #1 write_d1; + addr_d2 <= #1 addr_d1; + if(write_d2) + ram[addr_d2] = data; + end // always @ (posedge clock) + + data = (ce & read_d2) ? ram[addr_d2] : 36'bz; + + always @(posedge clock) + if(~ce & (write_d2 | write_d1 | wen)) + $display("$time ERROR: RAM CE not asserted during write cycle"); + +endmodule // ssram |