Remove usrp1 and usrp2 FPGA files. These are now hosted at:

git://ettus.sourcerepo.com/ettus/fpga.git

...under the 'usrp1' and 'usrp2' top-level directories.

1 files changed, 0 insertions, 24 deletions

diff --git a/usrp/fpga/models/fifo_4k.v b/usrp/fpga/models/fifo_4k.v
deleted file mode 100644
index 1fa4ba0a7..000000000
--- a/usrp/fpga/models/fifo_4k.v
+++ /dev/null
@@ -1,24 +0,0 @@
-
-
-module fifo_4k
-  (  input [15:0] data,
-     input 	wrreq,
-     input 	rdreq,
-     input 	rdclk,
-     input 	wrclk,
-     input 	aclr,
-     output [15:0] q,
-     output 	 rdfull,
-     output 	 rdempty,
-     output [11:0] rdusedw,
-     output 	 wrfull,
-     output 	 wrempty,
-     output [11:0]  wrusedw
-     );
-
-fifo #(.width(16),.depth(4096),.addr_bits(12)) fifo_4k 
-  ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
-    rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
-   
-endmodule // fifo_1k
-