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authorTom Rondeau2009-10-12 13:26:00 -0400
committerTom Rondeau2009-10-12 13:26:00 -0400
commitcd963d806b7f324fd845c7b51ef20985000b774c (patch)
tree9f21100ad438364dc2b6e5dc43e5553426febc97 /usrp/fpga/megacells/pll_bb.v
parentb5374350ea98bee6802976937f84ce91f1f721a6 (diff)
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Working DBPSK implementation with new PFB clock recovery block. The feedforward AGC wasn't playing nicely, the frequency aquistion range was increased to swing half the sample rate in either direction, and the number of filter phases to use was increased to 32.
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