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authorjcorgan2006-08-03 04:51:51 +0000
committerjcorgan2006-08-03 04:51:51 +0000
commit5d69a524f81f234b3fbc41d49ba18d6f6886baba (patch)
treeb71312bf7f1e8d10fef0f3ac6f28784065e73e72 /usrp/fpga/megacells/add32.cmp
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Houston, we have a trunk.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@3122 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'usrp/fpga/megacells/add32.cmp')
-rwxr-xr-xusrp/fpga/megacells/add32.cmp29
1 files changed, 29 insertions, 0 deletions
diff --git a/usrp/fpga/megacells/add32.cmp b/usrp/fpga/megacells/add32.cmp
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+--Copyright (C) 1991-2003 Altera Corporation
+--Any megafunction design, and related netlist (encrypted or decrypted),
+--support information, device programming or simulation file, and any other
+--associated documentation or information provided by Altera or a partner
+--under Altera's Megafunction Partnership Program may be used only
+--to program PLD devices (but not masked PLD devices) from Altera. Any
+--other use of such megafunction design, netlist, support information,
+--device programming or simulation file, or any other related documentation
+--or information is prohibited for any other purpose, including, but not
+--limited to modification, reverse engineering, de-compiling, or use with
+--any other silicon devices, unless such use is explicitly licensed under
+--a separate agreement with Altera or a megafunction partner. Title to the
+--intellectual property, including patents, copyrights, trademarks, trade
+--secrets, or maskworks, embodied in any such megafunction design, netlist,
+--support information, device programming or simulation file, or any other
+--related documentation or information provided by Altera or a megafunction
+--partner, remains with Altera, the megafunction partner, or their respective
+--licensors. No other licenses, including any licenses needed under any third
+--party's intellectual property, are provided herein.
+
+
+component add32
+ PORT
+ (
+ dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+ result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+ );
+end component;