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authoreb2008-04-30 03:52:31 +0000
committereb2008-04-30 03:52:31 +0000
commit9d1423b9506c89a51a10b6119d01ce9a82a13b0c (patch)
tree186e1b20618bf805dd262572bd3b2778b767d201 /usrp/fpga/inband_lib/packet_builder.v
parent7f202514385708941073930bc6d9a5237bb89826 (diff)
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Merged features/inband-usb -r6431:8293 into trunk.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@8295 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'usrp/fpga/inband_lib/packet_builder.v')
-rwxr-xr-xusrp/fpga/inband_lib/packet_builder.v84
1 files changed, 50 insertions, 34 deletions
diff --git a/usrp/fpga/inband_lib/packet_builder.v b/usrp/fpga/inband_lib/packet_builder.v
index fbf0a656e..2c9122394 100755
--- a/usrp/fpga/inband_lib/packet_builder.v
+++ b/usrp/fpga/inband_lib/packet_builder.v
@@ -1,8 +1,8 @@
-module packet_builder #(parameter NUM_CHAN = 1)(
+module packet_builder #(parameter NUM_CHAN = 2)(
// System
input rxclk,
input reset,
- input [31:0] adctime,
+ input [31:0] timestamp_clock,
input [3:0] channels,
// ADC side
input [15:0]chan_fifodata,
@@ -14,17 +14,17 @@ module packet_builder #(parameter NUM_CHAN = 1)(
output reg WR,
output reg [15:0]fifodata,
input have_space,
- input wire [31:0]rssi_0, input wire [31:0]rssi_1, input wire [31:0]rssi_2,
- input wire [31:0]rssi_3, output wire [7:0] debugbus,
- input [NUM_CHAN:0] overrun, input [NUM_CHAN:0] underrun);
+ input wire [31:0]rssi_0, input wire [31:0]rssi_1, input wire [31:0]rssi_2,
+ input wire [31:0]rssi_3, output wire [7:0] debugbus,
+ input [NUM_CHAN:0] underrun);
// States
`define IDLE 3'd0
`define HEADER1 3'd1
- `define HEADER2 3'd2
+ `define HEADER2 3'd2
`define TIMESTAMP 3'd3
- `define FORWARD 3'd4
+ `define FORWARD 3'd4
`define MAXPAYLOAD 504
@@ -39,51 +39,67 @@ module packet_builder #(parameter NUM_CHAN = 1)(
`define UNDERRUN 14
`define OVERRUN 15
+ reg [NUM_CHAN:0] overrun;
reg [2:0] state;
reg [8:0] read_length;
reg [8:0] payload_len;
- reg tstamp_complete;
+ reg timestamp_complete;
reg [3:0] check_next;
- wire [8:0] chan_used;
+
wire [31:0] true_rssi;
- wire [4:0] true_channel;
+ wire [4:0] true_channel;
+ wire ready_to_send;
+
+ assign debugbus = {chan_empty[0], rd_select[0], have_space,
+ (chan_usedw >= 10'd504), (chan_usedw ==0),
+ ready_to_send, state[1:0]};
- assign debugbus = {state, chan_empty[0], underrun[0], check_next[0],
- have_space, rd_select[0]};
- assign chan_used = chan_usedw[8:0];
- assign true_rssi = (rd_select[1]) ? ((rd_select[0]) ? rssi_3:rssi_2) :
+ assign true_rssi = (rd_select[1]) ? ((rd_select[0]) ? rssi_3:rssi_2) :
((rd_select[0]) ? rssi_1:rssi_0);
- assign true_channel = (check_next == 4'd0 ? 5'h1f : {1'd0, check_next - 4'd1});
+ assign true_channel = (check_next == 4'd0 ? 5'h1f : {1'd0, check_next - 4'd1});
+ assign ready_to_send = (chan_usedw >= 10'd504) || (chan_usedw == 0) ||
+ ((rd_select == NUM_CHAN)&&(chan_usedw > 0));
+
always @(posedge rxclk)
begin
if (reset)
begin
+ overrun <= 0;
WR <= 0;
rd_select <= 0;
chan_rdreq <= 0;
- tstamp_complete <= 0;
+ timestamp_complete <= 0;
check_next <= 0;
state <= `IDLE;
end
else case (state)
`IDLE: begin
- chan_rdreq <= #1 0;
- if (have_space)
- begin
- if(~chan_empty[check_next])
- begin
- state <= #1 `HEADER1;
- rd_select <= #1 check_next;
- end
- check_next <= #1 (check_next == channels ? 4'd0 : check_next + 4'd1);
- end
+ chan_rdreq <= #1 0;
+ //check if the channel is full
+ if(~chan_empty[check_next])
+ begin
+ if (have_space)
+ begin
+ //transmit if the usb buffer have space
+ //check if we should send
+ if (ready_to_send)
+ state <= #1 `HEADER1;
+
+ overrun[check_next] <= 0;
+ end
+ else
+ begin
+ state <= #1 `IDLE;
+ overrun[check_next] <= 1;
+ end
+ rd_select <= #1 check_next;
+ end
+ check_next <= #1 (check_next == channels ? 4'd0 : check_next + 4'd1);
end
`HEADER1: begin
- fifodata[`PAYLOAD_LEN] <= #1 (chan_used > 9'd252
- ? 9'd252 : chan_used << 1);
- payload_len <= #1 (chan_used > 9'd252
- ? 9'd252 : chan_used << 1);
+ fifodata[`PAYLOAD_LEN] <= #1 9'd504;
+ payload_len <= #1 9'd504;
fifodata[`TAG] <= #1 0;
fifodata[`MBZ] <= #1 0;
WR <= #1 1;
@@ -103,13 +119,13 @@ module packet_builder #(parameter NUM_CHAN = 1)(
end
`TIMESTAMP: begin
- fifodata <= #1 (tstamp_complete ? adctime[31:16] : adctime[15:0]);
- tstamp_complete <= #1 ~tstamp_complete;
+ fifodata <= #1 (timestamp_complete ? timestamp_clock[31:16] : timestamp_clock[15:0]);
+ timestamp_complete <= #1 ~timestamp_complete;
- if (~tstamp_complete)
+ if (~timestamp_complete)
chan_rdreq <= #1 1;
- state <= #1 (tstamp_complete ? `FORWARD : `TIMESTAMP);
+ state <= #1 (timestamp_complete ? `FORWARD : `TIMESTAMP);
end
`FORWARD: begin