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authorjcorgan2007-07-12 00:54:37 +0000
committerjcorgan2007-07-12 00:54:37 +0000
commitc39968a6c89b0d428eb25385bcc6306c8eeb8f26 (patch)
tree513ac6cee90d1fbbd0794d784c8c654dec58ee94 /usrp/firmware/include
parentd72cd723c56614f95286ed71272be3406cf36ddd (diff)
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Merged r5732:5941 from jcorgan/sar into trunk. Adds start of gr-radar-mono component. Trunk passes distcheck.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@5942 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'usrp/firmware/include')
-rw-r--r--usrp/firmware/include/fpga_regs_standard.h18
-rw-r--r--usrp/firmware/include/fpga_regs_standard.v18
2 files changed, 34 insertions, 2 deletions
diff --git a/usrp/firmware/include/fpga_regs_standard.h b/usrp/firmware/include/fpga_regs_standard.h
index 2f119fe65..6ae8b6cf2 100644
--- a/usrp/firmware/include/fpga_regs_standard.h
+++ b/usrp/firmware/include/fpga_regs_standard.h
@@ -185,7 +185,7 @@
// FIXME register numbers 50 to 63 are available
// ------------------------------------------------------------------------
-// Registers 64 to 79 are reserved for user custom FPGA builds.
+// Registers 64 to 95 are reserved for user custom FPGA builds.
// The standard USRP software will not touch these.
#define FR_USER_0 64
@@ -204,6 +204,22 @@
#define FR_USER_13 77
#define FR_USER_14 78
#define FR_USER_15 79
+#define FR_USER_16 80
+#define FR_USER_17 81
+#define FR_USER_18 82
+#define FR_USER_19 83
+#define FR_USER_20 84
+#define FR_USER_21 85
+#define FR_USER_22 86
+#define FR_USER_23 87
+#define FR_USER_24 88
+#define FR_USER_25 89
+#define FR_USER_26 90
+#define FR_USER_27 91
+#define FR_USER_28 92
+#define FR_USER_29 93
+#define FR_USER_30 94
+#define FR_USER_31 95
//Registers needed for multi usrp master/slave configuration
//
diff --git a/usrp/firmware/include/fpga_regs_standard.v b/usrp/firmware/include/fpga_regs_standard.v
index cc67be21a..b88bcddc1 100644
--- a/usrp/firmware/include/fpga_regs_standard.v
+++ b/usrp/firmware/include/fpga_regs_standard.v
@@ -157,7 +157,7 @@
// FIXME register numbers 50 to 63 are available
// ------------------------------------------------------------------------
-// Registers 64 to 79 are reserved for user custom FPGA builds.
+// Registers 64 to 95 are reserved for user custom FPGA builds.
// The standard USRP software will not touch these.
`define FR_USER_0 7'd64
@@ -176,6 +176,22 @@
`define FR_USER_13 7'd77
`define FR_USER_14 7'd78
`define FR_USER_15 7'd79
+`define FR_USER_16 7'd80
+`define FR_USER_17 7'd81
+`define FR_USER_18 7'd82
+`define FR_USER_19 7'd83
+`define FR_USER_20 7'd84
+`define FR_USER_21 7'd85
+`define FR_USER_22 7'd86
+`define FR_USER_23 7'd87
+`define FR_USER_24 7'd88
+`define FR_USER_25 7'd89
+`define FR_USER_26 7'd90
+`define FR_USER_27 7'd91
+`define FR_USER_28 7'd92
+`define FR_USER_29 7'd93
+`define FR_USER_30 7'd94
+`define FR_USER_31 7'd95
//Registers needed for multi usrp master/slave configuration
//