Adds capability to independently delay the Auto T/R switching signal

by a configurable number of clock ticks, to allow users to precisely
align their T/R output with the pipeline delays in the transmitter.

There are two new registers:

FR_ATR_TX_DELAY (7'd2)
FR_ATR_RX_DELAY (7'd3)

...and the corresponding db_base.py methods to set them:

db_base.set_atr_tx_delay(clock_ticks)
db_base.set_atr_rx_delay(clock_ticks)

These methods are inherited by all the daughterboard objects so you can
call them from your scripts as:

subdev.set_atr_tx_delay(...)

...where 'subdev' represents the daughtercard object you're working with.

The FPGA synthesis for the 2 RXHB, 2 TX case expands from 95% to 96%,
with no additional synthesis messages or impact on timing.



git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@5022 221aa14e-8319-0410-a670-987f0aec2ac5

1 files changed, 5 insertions, 2 deletions

diff --git a/usrp/firmware/include/fpga_regs_common.v b/usrp/firmware/include/fpga_regs_common.v
index ee87ac025..38f9362ee 100644
--- a/usrp/firmware/include/fpga_regs_common.v
+++ b/usrp/firmware/include/fpga_regs_common.v
@@ -13,8 +13,7 @@
 `define FR_TX_SAMPLE_RATE_DIV     7'd0
 `define FR_RX_SAMPLE_RATE_DIV     7'd1
 
-// 2 is available.
-// 3 is available.
+// 2 and 3 are defined in the ATR section
 
 `define FR_MASTER_CTRL            7'd4	// master enable and reset controls
 
@@ -112,3 +111,7 @@
 `define FR_ATR_TXVAL_3            7'd30
 `define FR_ATR_RXVAL_3            7'd31
 
+// Clock ticks to delay rising and falling edge of T/R signal
+`define FR_ATR_TX_DELAY           7'd2
+`define FR_ATR_RX_DELAY           7'd3
+