Adds capability to independently delay the Auto T/R switching signal

by a configurable number of clock ticks, to allow users to precisely
align their T/R output with the pipeline delays in the transmitter.

There are two new registers:

FR_ATR_TX_DELAY (7'd2)
FR_ATR_RX_DELAY (7'd3)

...and the corresponding db_base.py methods to set them:

db_base.set_atr_tx_delay(clock_ticks)
db_base.set_atr_rx_delay(clock_ticks)

These methods are inherited by all the daughterboard objects so you can
call them from your scripts as:

subdev.set_atr_tx_delay(...)

...where 'subdev' represents the daughtercard object you're working with.

The FPGA synthesis for the 2 RXHB, 2 TX case expands from 95% to 96%,
with no additional synthesis messages or impact on timing.



git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@5022 221aa14e-8319-0410-a670-987f0aec2ac5

1 files changed, 14 insertions, 0 deletions

diff --git a/gr-usrp/src/db_base.py b/gr-usrp/src/db_base.py
index 589af7546..d7bb0c30b 100644
--- a/gr-usrp/src/db_base.py
+++ b/gr-usrp/src/db_base.py
@@ -154,6 +154,20 @@ class db_base(object):
         """
         return self._u._write_fpga_reg(FR_ATR_RXVAL_0 + 3 * self._slot, v)
 
+    def set_atr_tx_delay(self, v):
+	"""
+	Set Auto T/R delay (in clock ticks) from when Tx fifo gets data to 
+	when T/R switches.
+	"""
+	return self._u._write_fpga_reg(FR_ATR_TX_DELAY, v)
+	
+    def set_atr_rx_delay(self, v):
+	"""
+	Set Auto T/R delay (in clock ticks) from when Tx fifo goes empty to 
+	when T/R switches.
+	"""
+	return self._u._write_fpga_reg(FR_ATR_RX_DELAY, v)
+	
     # derived classes should override the following methods
 
     def freq_range(self):