Merged r6045:6116 from jcorgan/radar into trunk. Updates gr-radar-mono with work-in-progress.

git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@6283 221aa14e-8319-0410-a670-987f0aec2ac5

15 files changed, 457 insertions, 268 deletions

diff --git a/gr-radar-mono/doc/registers.ods b/gr-radar-mono/doc/registers.ods
index 4213f8a59..7bafe2c58 100644
--- a/gr-radar-mono/doc/registers.ods
+++ b/gr-radar-mono/doc/registers.ods
diff --git a/gr-radar-mono/src/fpga/lib/Makefile.am b/gr-radar-mono/src/fpga/lib/Makefile.am
index d9f5174a2..8aefd754d 100644
--- a/gr-radar-mono/src/fpga/lib/Makefile.am
+++ b/gr-radar-mono/src/fpga/lib/Makefile.am
@@ -28,6 +28,7 @@ EXTRA_DIST = 			\
 		radar_tx.v	\
 		radar_rx.v	\
 		dac_interface.v	\
+		fifo32_4k.v	\
 		cordic_nco.v
 
 MOSTLYCLEANFILES = *~
diff --git a/gr-radar-mono/src/fpga/lib/fifo32_4k.v b/gr-radar-mono/src/fpga/lib/fifo32_4k.v
new file mode 100644
index 000000000..f31d020fd
--- /dev/null
+++ b/gr-radar-mono/src/fpga/lib/fifo32_4k.v
@@ -0,0 +1,161 @@
+// megafunction wizard: %FIFO%

+// GENERATION: STANDARD

+// VERSION: WM1.0

+// MODULE: scfifo 

+

+// ============================================================

+// File Name: fifo32_4k.v

+// Megafunction Name(s):

+// 			scfifo

+//

+// Simulation Library Files(s):

+// 			altera_mf

+// ============================================================

+// ************************************************************

+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!

+//

+// 7.1 Build 178 06/25/2007 SP 1 SJ Web Edition

+// ************************************************************

+

+

+//Copyright (C) 1991-2007 Altera Corporation

+//Your use of Altera Corporation's design tools, logic functions 

+//and other software and tools, and its AMPP partner logic 

+//functions, and any output files from any of the foregoing 

+//(including device programming or simulation files), and any 

+//associated documentation or information are expressly subject 

+//to the terms and conditions of the Altera Program License 

+//Subscription Agreement, Altera MegaCore Function License 

+//Agreement, or other applicable license agreement, including, 

+//without limitation, that your use is for the sole purpose of 

+//programming logic devices manufactured by Altera and sold by 

+//Altera or its authorized distributors.  Please refer to the 

+//applicable agreement for further details.

+

+

+// synopsys translate_off

+`timescale 1 ps / 1 ps

+// synopsys translate_on

+module fifo32_4k (

+	clock,

+	data,

+	rdreq,

+	sclr,

+	wrreq,

+	empty,

+	q);

+

+	input	  clock;

+	input	[31:0]  data;

+	input	  rdreq;

+	input	  sclr;

+	input	  wrreq;

+	output	  empty;

+	output	[31:0]  q;

+

+	wire  sub_wire0;

+	wire [31:0] sub_wire1;

+	wire  empty = sub_wire0;

+	wire [31:0] q = sub_wire1[31:0];

+

+	scfifo	scfifo_component (

+				.rdreq (rdreq),

+				.sclr (sclr),

+				.clock (clock),

+				.wrreq (wrreq),

+				.data (data),

+				.empty (sub_wire0),

+				.q (sub_wire1)

+				// synopsys translate_off

+				,

+				.aclr (),

+				.almost_empty (),

+				.almost_full (),

+				.full (),

+				.usedw ()

+				// synopsys translate_on

+				);

+	defparam

+		scfifo_component.add_ram_output_register = "OFF",

+		scfifo_component.intended_device_family = "Cyclone",

+		scfifo_component.lpm_numwords = 4096,

+		scfifo_component.lpm_showahead = "OFF",

+		scfifo_component.lpm_type = "scfifo",

+		scfifo_component.lpm_width = 32,

+		scfifo_component.lpm_widthu = 12,

+		scfifo_component.overflow_checking = "OFF",

+		scfifo_component.underflow_checking = "OFF",

+		scfifo_component.use_eab = "ON";

+

+

+endmodule

+

+// ============================================================

+// CNX file retrieval info

+// ============================================================

+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"

+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"

+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"

+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"

+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"

+// Retrieval info: PRIVATE: Clock NUMERIC "0"

+// Retrieval info: PRIVATE: Depth NUMERIC "4096"

+// Retrieval info: PRIVATE: Empty NUMERIC "1"

+// Retrieval info: PRIVATE: Full NUMERIC "0"

+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"

+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"

+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"

+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"

+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"

+// Retrieval info: PRIVATE: Optimize NUMERIC "2"

+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"

+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"

+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"

+// Retrieval info: PRIVATE: UsedW NUMERIC "0"

+// Retrieval info: PRIVATE: Width NUMERIC "32"

+// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"

+// Retrieval info: PRIVATE: diff_widths NUMERIC "0"

+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"

+// Retrieval info: PRIVATE: output_width NUMERIC "32"

+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"

+// Retrieval info: PRIVATE: rsFull NUMERIC "0"

+// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"

+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"

+// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"

+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"

+// Retrieval info: PRIVATE: wsFull NUMERIC "1"

+// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"

+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"

+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"

+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"

+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"

+// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"

+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"

+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"

+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"

+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"

+// Retrieval info: CONSTANT: USE_EAB STRING "ON"

+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock

+// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]

+// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty

+// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]

+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq

+// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL sclr

+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq

+// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0

+// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0

+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0

+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0

+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0

+// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0

+// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0

+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all

+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k.v TRUE

+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k.inc FALSE

+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k.cmp FALSE

+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k.bsf FALSE

+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k_inst.v FALSE

+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k_bb.v FALSE

+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k_waveforms.html TRUE

+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_4k_wave*.jpg TRUE

+// Retrieval info: LIB_FILE: altera_mf

diff --git a/gr-radar-mono/src/fpga/lib/radar.v b/gr-radar-mono/src/fpga/lib/radar.v
index 2a0c08bb5..127e9cee3 100644
--- a/gr-radar-mono/src/fpga/lib/radar.v
+++ b/gr-radar-mono/src/fpga/lib/radar.v
@@ -22,8 +22,8 @@
 `include "../lib/radar_config.vh"
 
 module radar(clk_i,saddr_i,sdata_i,s_strobe_i,
-	     tx_strobe_o,tx_dac_i_o,tx_dac_q_o,
-	     rx_strobe_i,rx_adc_i_i,rx_adc_q_i,
+	     tx_side_o,tx_strobe_o,tx_dac_i_o,tx_dac_q_o,
+	     rx_adc_i_i,rx_adc_q_i,
 	     rx_strobe_o,rx_ech_i_o,rx_ech_q_o);
 
    // System interface
@@ -33,12 +33,12 @@ module radar(clk_i,saddr_i,sdata_i,s_strobe_i,
    input 	 s_strobe_i;    // Configuration bus write
    
    // Transmit subsystem
+   output        tx_side_o;     // Transmitter slot
    output        tx_strobe_o;	// Generate an transmitter output sample
    output [13:0] tx_dac_i_o;	// I channel transmitter output to DAC
    output [13:0] tx_dac_q_o;    // Q channel transmitter output to DAC
-
+   
    // Receive subsystem
-   input         rx_strobe_i;	// Indicates receive sample ready from ADC
    input  [15:0] rx_adc_i_i;	// I channel input from ADC
    input  [15:0] rx_adc_q_i;	// Q channel input from ADC
    output 	 rx_strobe_o;	// Indicates output samples ready for Rx FIFO
@@ -47,6 +47,8 @@ module radar(clk_i,saddr_i,sdata_i,s_strobe_i,
 
    // Application control
    wire          reset;		// Master application reset
+   wire          tx_side;	// Transmitter slot
+   wire          debug_enabled; // Enable debugging mode; 	 
    wire 	 tx_enable;     // Transmitter enable
    wire 	 rx_enable;     // Receiver enable
    wire          tx_ctrl;       // Transmitter on control
@@ -59,7 +61,8 @@ module radar(clk_i,saddr_i,sdata_i,s_strobe_i,
 
    radar_control controller
      (.clk_i(clk_i),.saddr_i(saddr_i),.sdata_i(sdata_i),.s_strobe_i(s_strobe_i),
-      .reset_o(reset),.tx_strobe_o(tx_strobe_o),.tx_ctrl_o(tx_ctrl),.rx_ctrl_o(rx_ctrl),
+      .reset_o(reset),.tx_side_o(tx_side_o),.dbg_o(debug_enabled),
+      .tx_strobe_o(tx_strobe_o),.tx_ctrl_o(tx_ctrl),.rx_ctrl_o(rx_ctrl),
       .ampl_o(ampl),.fstart_o(fstart),.fincr_o(fincr));
 
    radar_tx transmitter
@@ -68,8 +71,8 @@ module radar(clk_i,saddr_i,sdata_i,s_strobe_i,
        .tx_i_o(tx_dac_i_o),.tx_q_o(tx_dac_q_o) );
    
    radar_rx receiver
-     ( .clk_i(clk_i),.rst_i(reset),.ena_i(rx_ctrl & 1'b0), // Disable receiver for now
-       .strobe_i(rx_strobe_i),.rx_in_i_i(rx_adc_i_i),.rx_in_q_i(rx_adc_q_i),
+     ( .clk_i(clk_i),.rst_i(reset),.ena_i(rx_ctrl),.dbg_i(debug_enabled),
+       .rx_in_i_i(rx_adc_i_i),.rx_in_q_i(rx_adc_q_i),
        .rx_strobe_o(rx_strobe_o),.rx_i_o(rx_ech_i_o),.rx_q_o(rx_ech_q_o) );
    
 endmodule // radar
diff --git a/gr-radar-mono/src/fpga/lib/radar_config.vh b/gr-radar-mono/src/fpga/lib/radar_config.vh
index a06a51119..251b2dba3 100644
--- a/gr-radar-mono/src/fpga/lib/radar_config.vh
+++ b/gr-radar-mono/src/fpga/lib/radar_config.vh
@@ -23,7 +23,13 @@
 `include "../../../../usrp/firmware/include/fpga_regs_standard.v"
 
 `define FR_RADAR_MODE           `FR_USER_0
-`define bmFR_RADAR_MODE_RESET	32'h0001
+`define bmFR_RADAR_MODE_RESET	32'b1 << 0
+`define bmFR_RADAR_TXSIDE       32'b1 << 1
+`define bmFR_RADAR_LOOP         32'b1 << 2
+`define bmFR_RADAR_META         32'b1 << 3
+`define bmFR_RADAR_DERAMP       32'b1 << 4
+`define bmFR_RADAR_CHIRPS       32'b11 << 5
+`define bmFR_RADAR_DEBUG        32'b1 << 7
 
 `define FR_RADAR_TON            `FR_USER_1
 `define FR_RADAR_TSW            `FR_USER_2
@@ -32,4 +38,3 @@
 `define FR_RADAR_AMPL           `FR_USER_5
 `define FR_RADAR_FSTART         `FR_USER_6
 `define FR_RADAR_FINCR          `FR_USER_7
-
diff --git a/gr-radar-mono/src/fpga/lib/radar_control.v b/gr-radar-mono/src/fpga/lib/radar_control.v
index 4f88645bb..e22da962d 100644
--- a/gr-radar-mono/src/fpga/lib/radar_control.v
+++ b/gr-radar-mono/src/fpga/lib/radar_control.v
@@ -22,7 +22,8 @@
 `include "../lib/radar_config.vh"
 
 module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,
-		     reset_o,tx_strobe_o,tx_ctrl_o,rx_ctrl_o,
+		     reset_o,tx_side_o,dbg_o,
+		     tx_strobe_o,tx_ctrl_o,rx_ctrl_o,
 		     ampl_o,fstart_o,fincr_o);
 
    // System interface
@@ -33,6 +34,8 @@ module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,
 
    // Control and configuration outputs
    output 	 reset_o;
+   output        tx_side_o;
+   output        dbg_o;
    output        tx_strobe_o;
    output        tx_ctrl_o;
    output        rx_ctrl_o;
@@ -42,8 +45,8 @@ module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,
    
    // Internal configuration
    wire 	 lp_ena;
-   wire 	 dr_ena;
    wire 	 md_ena;
+   wire 	 dr_ena;
    wire   [1:0]  chirps;
    wire   [15:0] t_on;
    wire   [15:0] t_sw;
@@ -51,9 +54,17 @@ module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,
    wire   [31:0] t_idle;
 
    // Configuration from host
+   wire [31:0] 	 mode;
    setting_reg #(`FR_RADAR_MODE)   sr_mode(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
-					   .out({chirps,md_ena,dr_ena,lp_ena,reset_o}));
-   				     
+					   .out(mode));
+   assign reset_o   = mode[0];
+   assign tx_side_o = mode[1];
+   assign lp_ena    = mode[2];
+   assign md_ena    = mode[3];
+   assign dr_ena    = mode[4];
+   assign chirps    = mode[6:5];
+   assign dbg_o     = mode[7];
+   
    setting_reg #(`FR_RADAR_TON)    sr_ton(.clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
 					  .out(t_on));
    
@@ -108,7 +119,7 @@ module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,
 		count <= 32'b0;
 	     end
 	   else
-	     count <= count + 24'b1;
+	     count <= count + 32'b1;
 
 	 `ST_LOOK:
 	   if (count == {16'b0,t_look})
@@ -123,7 +134,7 @@ module radar_control(clk_i,saddr_i,sdata_i,s_strobe_i,
 	   if (count == t_idle)
 	     begin
 		state <= `ST_ON;
-		count <= 24'b0;
+		count <= 32'b0;
 	     end
 	   else
 	     count <= count + 32'b1;
diff --git a/gr-radar-mono/src/fpga/lib/radar_rx.v b/gr-radar-mono/src/fpga/lib/radar_rx.v
index b559df699..1ca546134 100644
--- a/gr-radar-mono/src/fpga/lib/radar_rx.v
+++ b/gr-radar-mono/src/fpga/lib/radar_rx.v
@@ -22,43 +22,96 @@
 `include "../../../../usrp/firmware/include/fpga_regs_common.v"
 `include "../../../../usrp/firmware/include/fpga_regs_standard.v"
 
-module radar_rx(clk_i,rst_i,ena_i,strobe_i,saddr_i,sdata_i,s_strobe_i,
-		rx_in_i_i,rx_in_q_i,rx_i_o,rx_q_o,rx_strobe_o);
+module radar_rx(clk_i,rst_i,ena_i,dbg_i,
+		rx_in_i_i,rx_in_q_i,
+		rx_i_o,rx_q_o,rx_strobe_o);
    
    input clk_i;
    input rst_i;
    input ena_i;
-   input strobe_i;
-
-   input [6:0] saddr_i;
-   input [31:0] sdata_i;
-   input s_strobe_i;
-
+   input dbg_i;
+   
    input [15:0] rx_in_i_i;
    input [15:0] rx_in_q_i;
    
    output [15:0] rx_i_o;
    output [15:0] rx_q_o;
-   output rx_strobe_o;
+   output reg    rx_strobe_o;
 
-   // Just count up for debugging
-   reg [31:0] counter;
+   reg [15:0] count;
 
    always @(posedge clk_i)
-     begin
-	if (rst_i | ~ena_i)
-	  counter <= 32'b0;
-	else if (strobe_i & rx_strobe_o)
-	  counter <= counter + 32'b1;
-     end
+     if (rst_i | ~ena_i)
+       count <= 16'b0;
+     else
+       count <= count + 16'b1;
+
+   wire [31:0] fifo_data = dbg_i ? {count[15:0],16'hAA55} : {rx_in_i_i,rx_in_q_i};
+
+   // Need to buffer received samples as they come in at 32 bits per cycle
+   // but the rx_buffer.v fifo is only 16 bits wide.
+   //
+   reg         fifo_read;
+   wire [31:0] fifo_out;
+   wire        fifo_empty;
+   
+   fifo32_4k fifo(.clock(clk_i),.sclr(rst_i),
+		  .data(fifo_data),.wrreq(ena_i),
+		  .q(fifo_out),.rdreq(fifo_read),
+		  .empty(fifo_empty) );
+
+   `define ST_RD_IDLE     4'b0001
+   `define ST_RD_REQ      4'b0010
+   `define ST_WR_FIFO     4'b0100
+   `define ST_RD_DELAY    4'b1000
+
+   reg [3:0] state;
+   reg [3:0] delay;
+   
+   always @(posedge clk_i)
+     if (rst_i | ~ena_i)
+       begin
+	  state <= `ST_RD_IDLE;
+	  delay <= 4'd0;
+	  rx_strobe_o <= 1'b0;
+	  fifo_read <= 1'b0;
+       end
+     else
+       case (state)
+	 `ST_RD_IDLE:
+	   begin
+	      if (!fifo_empty)
+		begin
+		   fifo_read <= 1'b1;
+		   state <= `ST_RD_REQ;
+		end
+	   end
+
+	 `ST_RD_REQ:
+	   begin
+	      fifo_read <= 1'b0;
+	      rx_strobe_o <= 1'b1;
+	      state <= `ST_WR_FIFO;
+	   end
+
+	 `ST_WR_FIFO:
+	   begin
+	      rx_strobe_o <= 1'b0;
+	      state <= `ST_RD_DELAY;
+	   end
+
+	 `ST_RD_DELAY:
+	   if (delay == 7)
+	     begin
+		delay <= 0;
+		state <= `ST_RD_IDLE;
+	     end
+	   else
+	     delay <= delay + 1'b1;
 
-   assign rx_i_o = ena_i ? counter[31:16] : 16'b0;
-   assign rx_q_o = ena_i ? counter[15:0] : 16'b0;
+       endcase // case(state)
    
-   // Temporarily we duplicate what master_control.v did to generate decim_strobe
-   // so we can do receive debugging. Later we'll drive rx_strobe_o in bursts to
-   // load receiver data into the rx fifo.
-   strobe_gen rx_strobe_gen
-     ( .clock(clk_i),.reset(rst_i),.enable(ena_i),.rate(7),.strobe_in(strobe_i),.strobe(rx_strobe_o) );
+   assign rx_i_o = fifo_out[31:16];
+   assign rx_q_o = fifo_out[15:0];
    
 endmodule // radar_rx
diff --git a/gr-radar-mono/src/fpga/tb/radar_tb.sav b/gr-radar-mono/src/fpga/tb/radar_tb.sav
index dbc321fce..aaf2ffd03 100644
--- a/gr-radar-mono/src/fpga/tb/radar_tb.sav
+++ b/gr-radar-mono/src/fpga/tb/radar_tb.sav
@@ -1,4 +1,4 @@
-*-24.712317 37100000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-24.808464 9235000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 @28
 radar_tb.clk
 radar_tb.ena
@@ -24,3 +24,11 @@ radar_tb.uut.tx_dac_q_o[13:0]
 @28
 radar_tb.uut.controller.tx_ctrl_o
 radar_tb.uut.controller.rx_ctrl_o
+@200
+-
+@28
+radar_tb.fifo_strobe
+@8025
+radar_tb.fifo_i[15:0]
+@22
+radar_tb.fifo_q[15:0]
diff --git a/gr-radar-mono/src/fpga/tb/radar_tb.v b/gr-radar-mono/src/fpga/tb/radar_tb.v
index 0620582e6..cb26abf5e 100644
--- a/gr-radar-mono/src/fpga/tb/radar_tb.v
+++ b/gr-radar-mono/src/fpga/tb/radar_tb.v
@@ -41,7 +41,6 @@ module radar_tb;
    wire [13:0] tx_dac_q;
 
    // ADC bus
-   reg         rx_strobe;
    reg [15:0]  rx_adc_i;
    reg [15:0]  rx_adc_q;
    
@@ -56,7 +55,7 @@ module radar_tb;
    radar uut
      (.clk_i(clk),.saddr_i(saddr),.sdata_i(sdata),.s_strobe_i(s_strobe),
       .tx_strobe_o(tx_strobe),.tx_dac_i_o(tx_dac_i),.tx_dac_q_o(tx_dac_q),
-      .rx_strobe_i(rx_strobe),.rx_adc_i_i(rx_adc_i),.rx_adc_q_i(rx_adc_q),
+      .rx_adc_i_i(rx_adc_i),.rx_adc_q_i(rx_adc_q),
       .rx_strobe_o(fifo_strobe),.rx_ech_i_o(fifo_i),.rx_ech_q_o(fifo_q));
 
    // Start up initialization
@@ -68,7 +67,6 @@ module radar_tb;
 	saddr = 0;
 	sdata = 0;
 	s_strobe = 0;
-	rx_strobe = 1;
 	rx_adc_i = 0;
 	rx_adc_q = 0;
 	mode = 0;
@@ -187,8 +185,8 @@ module radar_tb;
 
 	 #20 set_ton(320-1);	// 5us on time
 	 #20 set_tsw(26-1);	// 406ns switching time
-	 #20 set_tlook(320-1);  // 5us look time
-	 #20 set_tidle(3174-1); // 60us pulse period
+	 #20 set_tlook(640-1);  // 10us look time
+	 #20 set_tidle(2854-1); // 60us pulse period
 	 
 	 #20 set_ampl(16'd9946);
 	 #20 set_fstart(32'h80000000); // -16 to 16 MHz
diff --git a/gr-radar-mono/src/fpga/top/usrp_radar_mono.qsf b/gr-radar-mono/src/fpga/top/usrp_radar_mono.qsf
index 901e1e0bb..d1db2e9cf 100644
--- a/gr-radar-mono/src/fpga/top/usrp_radar_mono.qsf
+++ b/gr-radar-mono/src/fpga/top/usrp_radar_mono.qsf
@@ -29,29 +29,7 @@
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04  JULY 13, 2003"
 set_global_assignment -name LAST_QUARTUS_VERSION "7.1 SP1"
-set_global_assignment -name VERILOG_FILE usrp_radar_mono.v
-set_global_assignment -name VERILOG_FILE dacpll.v
-set_global_assignment -name VERILOG_FILE ../lib/cordic_nco.v
-set_global_assignment -name VERILOG_FILE ../lib/dac_interface.v
-set_global_assignment -name VERILOG_FILE ../lib/radar_control.v
-set_global_assignment -name VERILOG_FILE ../lib/radar_rx.v
-set_global_assignment -name VERILOG_FILE ../lib/radar_tx.v
-set_global_assignment -name VERILOG_FILE ../lib/radar.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/adc_interface.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/atr_delay.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/bidir_reg.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/clk_divider.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cordic_stage.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cordic.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/gen_sync.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/io_pins.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/master_control.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rssi.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rx_buffer.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rx_dcoffset.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/serial_io.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/setting_reg.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/strobe_gen.v
+set_global_assignment -name MESSAGE_SUPPRESSION_RULE_FILE usrp_radar_mono.srf
 
 # Pin & Location Assignments
 # ==========================
@@ -349,7 +327,7 @@ set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF
 	# Classic Timing Assignments
 	# ==========================
 set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK
-	set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK
+set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK
 
 # end CLOCK(SCLK)
 # ---------------
@@ -360,7 +338,7 @@ set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK
 	# Classic Timing Assignments
 	# ==========================
 set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk
-	set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk
+set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk
 
 # end CLOCK(master_clk)
 # ---------------------
@@ -371,31 +349,54 @@ set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk
 	# Classic Timing Assignments
 	# ==========================
 set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk
-	set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk
+set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk
 
 # end CLOCK(usbclk)
 # -----------------
 
-# ----------------------
+# -----------------------------
 # start ENTITY(usrp_radar_mono)
 
 	# Classic Timing Assignments
 	# ==========================
-	set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK
-	set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk
-	set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk
+set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK
+set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk
+set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk
 
 	# start DESIGN_PARTITION(Top)
 	# ---------------------------
 
 		# Incremental Compilation Assignments
 		# ===================================
-		set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
-		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 
 	# end DESIGN_PARTITION(Top)
 	# -------------------------
 
 # end ENTITY(usrp_radar_mono)
-# --------------------
-set_global_assignment -name MESSAGE_SUPPRESSION_RULE_FILE usrp_radar_mono.srf
\ No newline at end of file
+# ---------------------------
+set_global_assignment -name VERILOG_FILE usrp_radar_mono.v
+set_global_assignment -name VERILOG_FILE dacpll.v
+set_global_assignment -name VERILOG_FILE ../lib/cordic_nco.v
+set_global_assignment -name VERILOG_FILE ../lib/dac_interface.v
+set_global_assignment -name VERILOG_FILE ../lib/fifo32_4k.v
+set_global_assignment -name VERILOG_FILE ../lib/radar_control.v
+set_global_assignment -name VERILOG_FILE ../lib/radar_rx.v
+set_global_assignment -name VERILOG_FILE ../lib/radar_tx.v
+set_global_assignment -name VERILOG_FILE ../lib/radar.v
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/adc_interface.v
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/atr_delay.v
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/bidir_reg.v
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/clk_divider.v
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cordic_stage.v
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cordic.v
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/gen_sync.v
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/io_pins.v
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/master_control.v
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rssi.v
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rx_buffer.v
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rx_dcoffset.v
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/serial_io.v
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/setting_reg.v
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/strobe_gen.v
\ No newline at end of file
diff --git a/gr-radar-mono/src/fpga/top/usrp_radar_mono.rbf b/gr-radar-mono/src/fpga/top/usrp_radar_mono.rbf
index 0d4bfcdfa..f36c3ac76 100644
--- a/gr-radar-mono/src/fpga/top/usrp_radar_mono.rbf
+++ b/gr-radar-mono/src/fpga/top/usrp_radar_mono.rbf
diff --git a/gr-radar-mono/src/fpga/top/usrp_radar_mono.srf b/gr-radar-mono/src/fpga/top/usrp_radar_mono.srf
index ebf4bce8f..e5645322b 100644
--- a/gr-radar-mono/src/fpga/top/usrp_radar_mono.srf
+++ b/gr-radar-mono/src/fpga/top/usrp_radar_mono.srf
@@ -1,8 +1,5 @@
 { "Warning" "WSGN_SEARCH_FILE" "../../../../../trunk/usrp/fpga/megacells/bustri.v 1 1 " "Warning: Using design file ../../../../../trunk/usrp/fpga/megacells/bustri.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" {  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 1 0 "" 0}

 { "Warning" "WSGN_SEARCH_FILE" "../../../../../trunk/usrp/fpga/megacells/fifo_4k.v 10 10 " "Warning: Using design file ../../../../../trunk/usrp/fpga/megacells/fifo_4k.v, which is not specified as a design file for the current project, but contains definitions for 10 design units and 10 entities in project" {  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 1 0 "" 0}

-{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "write_done serial_io.v(48) " "Warning (10036): Verilog HDL or VHDL warning at serial_io.v(48): object \"write_done\" assigned a value but never read" {  } { { "../../../../usrp/fpga/sdr_lib/serial_io.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/serial_io.v" 48 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 1 0 "" 0}

-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 atr_delay.v(58) " "Warning (10230): Verilog HDL assignment warning at atr_delay.v(58): truncated value with size 32 to match size of target (12)" {  } { { "../../../../usrp/fpga/sdr_lib/atr_delay.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/atr_delay.v" 58 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 1 0 "" 0}

-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 atr_delay.v(71) " "Warning (10230): Verilog HDL assignment warning at atr_delay.v(71): truncated value with size 32 to match size of target (12)" {  } { { "../../../../usrp/fpga/sdr_lib/atr_delay.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/atr_delay.v" 71 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 1 0 "" 0}

 { "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_rx_delay 12 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_rx_delay\" is connected to a signal of width 12. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_rx_delay" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 138 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}

 { "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_tx_delay 12 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_tx_delay\" is connected to a signal of width 12. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_tx_delay" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 137 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}

 { "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_atr_rxval_3 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_atr_rxval_3\" is connected to a signal of width 16. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_atr_rxval_3" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 134 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}

@@ -29,7 +26,6 @@
 { "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_decim 8 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_decim\" is connected to a signal of width 8. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_decim" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 51 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}

 { "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_interp 8 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_interp\" is connected to a signal of width 8. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_interp" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 50 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}

 { "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_mstr_ctrl 8 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_mstr_ctrl\" is connected to a signal of width 8. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../../../../usrp/fpga/sdr_lib/master_control.v" "sr_mstr_ctrl" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/master_control.v" 42 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}

-{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "rate rx_strobe_gen 32 8 " "Warning: Port \"rate\" on the entity instantiation of \"rx_strobe_gen\" is connected to a signal of width 32. The formal width of the signal in the module is 8.  Extra bits will be ignored." {  } { { "../lib/radar_rx.v" "rx_strobe_gen" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_rx.v" 62 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be ignored." 1 0 "" 0}

 { "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage11 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage11\" is connected to a signal of width 16. The formal width of the signal in the module is 15.  Extra bits will be ignored." {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage11" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 100 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be ignored." 1 0 "" 0}

 { "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage10 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage10\" is connected to a signal of width 16. The formal width of the signal in the module is 15.  Extra bits will be ignored." {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage10" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 99 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be ignored." 1 0 "" 0}

 { "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage9 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage9\" is connected to a signal of width 16. The formal width of the signal in the module is 15.  Extra bits will be ignored." {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage9" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 98 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be ignored." 1 0 "" 0}

@@ -42,99 +38,28 @@
 { "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage2 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage2\" is connected to a signal of width 16. The formal width of the signal in the module is 15.  Extra bits will be ignored." {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage2" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 91 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be ignored." 1 0 "" 0}

 { "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage1 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage1\" is connected to a signal of width 16. The formal width of the signal in the module is 15.  Extra bits will be ignored." {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage1" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 90 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be ignored." 1 0 "" 0}

 { "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "ordered port 6 cordic_stage0 16 15 " "Warning: Port \"ordered port 6\" on the entity instantiation of \"cordic_stage0\" is connected to a signal of width 16. The formal width of the signal in the module is 15.  Extra bits will be ignored." {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "cordic_stage0" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 89 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be ignored." 1 0 "" 0}

-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_ampl 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_ampl\" is connected to a signal of width 16. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../lib/radar_control.v" "sr_ampl" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 59 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}

-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_mode 8 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_mode\" is connected to a signal of width 8. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../lib/radar_control.v" "sr_mode" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 56 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}

-{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Warning: The following nets are missing source, defaulting to GND" {  } {  } 0 0 "The following nets are missing source, defaulting to GND" 1 0 "" 0}

-{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Warning: The following nets are missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "radar:radar_mono\|radar_control:controller\|rst_i " "Warning: Net \"radar:radar_mono\|radar_control:controller\|rst_i\"" {  } { { "../lib/radar_control.v" "rst_i" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 55 -1 0 } }  } 0 0 "Net \"%1!s!\"" 1 0 "" 0}  } {  } 0 0 "The following nets are missing source, defaulting to GND" 0 0 "" 0}

+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_ampl 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_ampl\" is connected to a signal of width 16. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../lib/radar_control.v" "sr_ampl" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 81 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}

+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_tlook 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_tlook\" is connected to a signal of width 16. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../lib/radar_control.v" "sr_tlook" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 75 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}

+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_tsw 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_tsw\" is connected to a signal of width 16. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../lib/radar_control.v" "sr_tsw" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 72 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}

+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_ton 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_ton\" is connected to a signal of width 16. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../lib/radar_control.v" "sr_ton" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 69 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}

 { "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_rxformat 11 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_rxformat\" is connected to a signal of width 11. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../../../../usrp/fpga/sdr_lib/rx_buffer.v" "sr_rxformat" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/rx_buffer.v" 66 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}

 { "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_rxmux 20 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_rxmux\" is connected to a signal of width 20. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../../../../usrp/fpga/sdr_lib/adc_interface.v" "sr_rxmux" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/adc_interface.v" 54 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}

 { "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_dco_en 4 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_dco_en\" is connected to a signal of width 4. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../../../../usrp/fpga/sdr_lib/adc_interface.v" "sr_dco_en" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/adc_interface.v" 32 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}

 { "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[0\] data_in GND " "Warning: Reduced register \"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[0\]\" with stuck data_in port to stuck value GND" {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}

 { "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[1\] data_in GND " "Warning: Reduced register \"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[1\]\" with stuck data_in port to stuck value GND" {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}

-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[2\] data_in GND " "Warning: Reduced register \"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[2\]\" with stuck data_in port to stuck value GND" {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}

-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[3\] data_in GND " "Warning: Reduced register \"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[3\]\" with stuck data_in port to stuck value GND" {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}

-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[4\] data_in GND " "Warning: Reduced register \"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[4\]\" with stuck data_in port to stuck value GND" {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}

-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[5\] data_in GND " "Warning: Reduced register \"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[5\]\" with stuck data_in port to stuck value GND" {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}

-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[6\] data_in GND " "Warning: Reduced register \"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[6\]\" with stuck data_in port to stuck value GND" {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}

-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[7\] data_in GND " "Warning: Reduced register \"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[7\]\" with stuck data_in port to stuck value GND" {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}

-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[8\] data_in GND " "Warning: Reduced register \"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[8\]\" with stuck data_in port to stuck value GND" {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}

-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[9\] data_in GND " "Warning: Reduced register \"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[9\]\" with stuck data_in port to stuck value GND" {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}

-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[10\] data_in GND " "Warning: Reduced register \"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[10\]\" with stuck data_in port to stuck value GND" {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}

-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[11\] data_in GND " "Warning: Reduced register \"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[11\]\" with stuck data_in port to stuck value GND" {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}

-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[12\] data_in GND " "Warning: Reduced register \"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[12\]\" with stuck data_in port to stuck value GND" {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}

-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[13\] data_in GND " "Warning: Reduced register \"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[13\]\" with stuck data_in port to stuck value GND" {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}

-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[14\] data_in GND " "Warning: Reduced register \"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[14\]\" with stuck data_in port to stuck value GND" {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}

-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[15\] data_in GND " "Warning: Reduced register \"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[15\]\" with stuck data_in port to stuck value GND" {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}

-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[16\] data_in GND " "Warning: Reduced register \"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[16\]\" with stuck data_in port to stuck value GND" {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}

-{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[17\] data_in GND " "Warning: Reduced register \"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[17\]\" with stuck data_in port to stuck value GND" {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}

 { "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "master_control:master_control\|atr_delay:atr_delay\|state.0001 data_in GND " "Warning: Reduced register \"master_control:master_control\|atr_delay:atr_delay\|state.0001\" with stuck data_in port to stuck value GND" {  } { { "../../../../usrp/fpga/sdr_lib/atr_delay.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/atr_delay.v" 31 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}

 { "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "MYSTERY_SIGNAL GND " "Warning: Pin \"MYSTERY_SIGNAL\" stuck at GND" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 24 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}

 { "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "FX2_3 GND " "Warning: Pin \"FX2_3\" stuck at GND" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 33 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}

-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[0\] GND " "Warning: Pin \"tx_b\[0\]\" stuck at GND" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}

-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[1\] GND " "Warning: Pin \"tx_b\[1\]\" stuck at GND" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}

-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[2\] GND " "Warning: Pin \"tx_b\[2\]\" stuck at GND" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}

-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[3\] GND " "Warning: Pin \"tx_b\[3\]\" stuck at GND" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}

-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[4\] GND " "Warning: Pin \"tx_b\[4\]\" stuck at GND" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}

-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[5\] GND " "Warning: Pin \"tx_b\[5\]\" stuck at GND" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}

-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[6\] GND " "Warning: Pin \"tx_b\[6\]\" stuck at GND" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}

-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[7\] GND " "Warning: Pin \"tx_b\[7\]\" stuck at GND" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}

-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[8\] GND " "Warning: Pin \"tx_b\[8\]\" stuck at GND" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}

-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[9\] GND " "Warning: Pin \"tx_b\[9\]\" stuck at GND" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}

-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[10\] GND " "Warning: Pin \"tx_b\[10\]\" stuck at GND" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}

-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[11\] GND " "Warning: Pin \"tx_b\[11\]\" stuck at GND" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}

-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[12\] GND " "Warning: Pin \"tx_b\[12\]\" stuck at GND" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}

-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "tx_b\[13\] GND " "Warning: Pin \"tx_b\[13\]\" stuck at GND" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}

-{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "TXSYNC_B GND " "Warning: Pin \"TXSYNC_B\" stuck at GND" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 44 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}

 { "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "usbrdy\[0\] GND " "Warning: Pin \"usbrdy\[0\]\" stuck at GND" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 49 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 1 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}

-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design contains * input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[0\] " "Warning: No output dependent on input pin \"rx_b_a\[0\]\"" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}

-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design contains * input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[1\] " "Warning: No output dependent on input pin \"rx_b_a\[1\]\"" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}

-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design contains * input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[2\] " "Warning: No output dependent on input pin \"rx_b_a\[2\]\"" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}

-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design contains * input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[3\] " "Warning: No output dependent on input pin \"rx_b_a\[3\]\"" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}

-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design contains * input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[4\] " "Warning: No output dependent on input pin \"rx_b_a\[4\]\"" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}

-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design contains * input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[5\] " "Warning: No output dependent on input pin \"rx_b_a\[5\]\"" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}

-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design contains * input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[6\] " "Warning: No output dependent on input pin \"rx_b_a\[6\]\"" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}

-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design contains * input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[7\] " "Warning: No output dependent on input pin \"rx_b_a\[7\]\"" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}

-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design contains * input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[8\] " "Warning: No output dependent on input pin \"rx_b_a\[8\]\"" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}

-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design contains * input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[9\] " "Warning: No output dependent on input pin \"rx_b_a\[9\]\"" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}

-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design contains * input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[10\] " "Warning: No output dependent on input pin \"rx_b_a\[10\]\"" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}

-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design contains * input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_a\[11\] " "Warning: No output dependent on input pin \"rx_b_a\[11\]\"" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 36 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}

-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design contains * input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[0\] " "Warning: No output dependent on input pin \"rx_b_b\[0\]\"" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}

-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design contains * input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[1\] " "Warning: No output dependent on input pin \"rx_b_b\[1\]\"" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}

-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design contains * input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[2\] " "Warning: No output dependent on input pin \"rx_b_b\[2\]\"" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}

-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design contains * input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[3\] " "Warning: No output dependent on input pin \"rx_b_b\[3\]\"" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}

-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design contains * input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[4\] " "Warning: No output dependent on input pin \"rx_b_b\[4\]\"" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}

-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design contains * input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[5\] " "Warning: No output dependent on input pin \"rx_b_b\[5\]\"" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}

-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design contains * input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[6\] " "Warning: No output dependent on input pin \"rx_b_b\[6\]\"" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}

-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design contains * input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[7\] " "Warning: No output dependent on input pin \"rx_b_b\[7\]\"" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}

-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design contains * input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[8\] " "Warning: No output dependent on input pin \"rx_b_b\[8\]\"" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}

-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design contains * input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[9\] " "Warning: No output dependent on input pin \"rx_b_b\[9\]\"" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}

-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design contains * input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[10\] " "Warning: No output dependent on input pin \"rx_b_b\[10\]\"" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}

-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "49 " "Warning: Design contains * input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "rx_b_b\[11\] " "Warning: No output dependent on input pin \"rx_b_b\[11\]\"" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 38 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}

-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning: Following * pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "MYSTERY_SIGNAL GND " "Info: Pin MYSTERY_SIGNAL has GND driving its datain port" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 24 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "MYSTERY_SIGNAL" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { MYSTERY_SIGNAL } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { MYSTERY_SIGNAL } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 1 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}

-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning: Following * pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FX2_3 GND " "Info: Pin FX2_3 has GND driving its datain port" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 33 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FX2_3" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { FX2_3 } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { FX2_3 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 1 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}

-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning: Following * pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[0\] GND " "Info: Pin tx_b\[0\] has GND driving its datain port" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[0\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[0] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 1 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}

-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning: Following * pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[1\] GND " "Info: Pin tx_b\[1\] has GND driving its datain port" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[1\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[1] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 1 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}

-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning: Following * pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[2\] GND " "Info: Pin tx_b\[2\] has GND driving its datain port" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[2\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[2] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 1 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}

-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning: Following * pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[3\] GND " "Info: Pin tx_b\[3\] has GND driving its datain port" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[3\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[3] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 1 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}

-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning: Following * pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[4\] GND " "Info: Pin tx_b\[4\] has GND driving its datain port" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[4\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[4] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 1 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}

-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning: Following * pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[5\] GND " "Info: Pin tx_b\[5\] has GND driving its datain port" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[5\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[5] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 1 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}

-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning: Following * pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[6\] GND " "Info: Pin tx_b\[6\] has GND driving its datain port" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[6\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[6] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 1 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}

-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning: Following * pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[7\] GND " "Info: Pin tx_b\[7\] has GND driving its datain port" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[7\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[7] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 1 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}

-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning: Following * pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[8\] GND " "Info: Pin tx_b\[8\] has GND driving its datain port" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[8\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[8] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 1 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}

-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning: Following * pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[9\] GND " "Info: Pin tx_b\[9\] has GND driving its datain port" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[9\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[9] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 1 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}

-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning: Following * pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[10\] GND " "Info: Pin tx_b\[10\] has GND driving its datain port" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[10\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[10] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 1 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}

-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning: Following * pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[11\] GND " "Info: Pin tx_b\[11\] has GND driving its datain port" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[11\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[11] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 1 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}

-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning: Following * pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[12\] GND " "Info: Pin tx_b\[12\] has GND driving its datain port" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[12\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[12] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 1 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}

-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning: Following * pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "tx_b\[13\] GND " "Info: Pin tx_b\[13\] has GND driving its datain port" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 41 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "tx_b\[13\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[13] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { tx_b[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 1 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}

-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning: Following * pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "TXSYNC_B GND " "Info: Pin TXSYNC_B has GND driving its datain port" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 44 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "TXSYNC_B" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { TXSYNC_B } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { TXSYNC_B } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 1 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}

-{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "18 " "Warning: Following * pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "usbrdy\[0\] GND " "Info: Pin usbrdy\[0\] has GND driving its datain port" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 49 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "usbrdy\[0\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { usbrdy[0] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { usbrdy[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 1 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}

-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_ampl 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_ampl\" is connected to a signal of width 16. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../lib/radar_control.v" "sr_ampl" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 69 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}

-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_tlook 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_tlook\" is connected to a signal of width 16. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../lib/radar_control.v" "sr_tlook" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 63 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}

-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_tsw 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_tsw\" is connected to a signal of width 16. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../lib/radar_control.v" "sr_tsw" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 60 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}

-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_ton 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_ton\" is connected to a signal of width 16. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../lib/radar_control.v" "sr_ton" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 57 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}

-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_mode 6 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_mode\" is connected to a signal of width 6. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../lib/radar_control.v" "sr_mode" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 54 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}

-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_ampl 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_ampl\" is connected to a signal of width 16. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../lib/radar_control.v" "sr_ampl" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 70 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}

-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_tlook 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_tlook\" is connected to a signal of width 16. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../lib/radar_control.v" "sr_tlook" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 64 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}

-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_tsw 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_tsw\" is connected to a signal of width 16. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../lib/radar_control.v" "sr_tsw" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 61 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}

-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_ton 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_ton\" is connected to a signal of width 16. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../lib/radar_control.v" "sr_ton" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 58 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}

-{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_mode 6 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_mode\" is connected to a signal of width 6. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../lib/radar_control.v" "sr_mode" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 55 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}

+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Warning: Design contains * input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "usbctl\[0\] " "Warning: No output dependent on input pin \"usbctl\[0\]\"" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 48 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 1 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}

+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "3 " "Warning: Following * pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "MYSTERY_SIGNAL GND " "Info: Pin MYSTERY_SIGNAL has GND driving its datain port" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 24 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "MYSTERY_SIGNAL" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { MYSTERY_SIGNAL } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { MYSTERY_SIGNAL } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 1 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}

+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "3 " "Warning: Following * pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FX2_3 GND " "Info: Pin FX2_3 has GND driving its datain port" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 33 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "FX2_3" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { FX2_3 } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { FX2_3 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 1 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}

+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "3 " "Warning: Following * pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "usbrdy\[0\] GND " "Info: Pin usbrdy\[0\] has GND driving its datain port" {  } { { "usrp_radar_mono.v" "" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/top/usrp_radar_mono.v" 49 -1 0 } } { "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "usbrdy\[0\]" } } } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { usbrdy[0] } "NODE_NAME" } } { "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { usbrdy[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 1 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}

+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_ampl 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_ampl\" is connected to a signal of width 16. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../lib/radar_control.v" "sr_ampl" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 79 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}

+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_tlook 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_tlook\" is connected to a signal of width 16. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../lib/radar_control.v" "sr_tlook" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 73 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}

+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_tsw 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_tsw\" is connected to a signal of width 16. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../lib/radar_control.v" "sr_tsw" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 70 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}

+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_ton 16 32 " "Warning: Port \"out\" on the entity instantiation of \"sr_ton\" is connected to a signal of width 16. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic." {  } { { "../lib/radar_control.v" "sr_ton" { Text "H:/gnuradio/radar/gr-radar-mono/src/fpga/lib/radar_control.v" 67 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 1 0 "" 0}

+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 atr_delay.v(58) " "Warning (10230): Verilog HDL assignment warning at atr_delay.v(58): truncated value with size 32 to match size of target (12)" {  } { { "../../../../usrp/fpga/sdr_lib/atr_delay.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/atr_delay.v" 58 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 1 0 "" 0}

+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 atr_delay.v(71) " "Warning (10230): Verilog HDL assignment warning at atr_delay.v(71): truncated value with size 32 to match size of target (12)" {  } { { "../../../../usrp/fpga/sdr_lib/atr_delay.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/atr_delay.v" 71 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 1 0 "" 0}

+{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "write_done serial_io.v(48) " "Warning (10036): Verilog HDL or VHDL warning at serial_io.v(48): object \"write_done\" assigned a value but never read" {  } { { "../../../../usrp/fpga/sdr_lib/serial_io.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/serial_io.v" 48 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 1 0 "" 0}

+{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[2\] data_in GND " "Warning: Reduced register \"radar:radar_mono\|radar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[2\]\" with stuck data_in port to stuck value GND" {  } { { "../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text "H:/gnuradio/radar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0 "" 0}

diff --git a/gr-radar-mono/src/fpga/top/usrp_radar_mono.v b/gr-radar-mono/src/fpga/top/usrp_radar_mono.v
index 891af2353..f6f862938 100644
--- a/gr-radar-mono/src/fpga/top/usrp_radar_mono.v
+++ b/gr-radar-mono/src/fpga/top/usrp_radar_mono.v
@@ -95,28 +95,30 @@ module usrp_radar_mono
    ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
    // Transmit Side
    
+   wire        tx_side;
    wire [13:0] tx_i, tx_q;
    wire [13:0] tx_dac;
+   wire        tx_sync;
    
    dac_interface dac(.clk_i(clk64),.rst_i(tx_dsp_reset),.ena_i(enable_tx),
 		     .strobe_i(tx_sample_strobe),.tx_i_i(tx_i),.tx_q_i(tx_q),
-		     .tx_data_o(tx_dac),.tx_sync_o(TXSYNC_A));
+		     .tx_data_o(tx_dac),.tx_sync_o(tx_sync));
 
-   assign tx_a = tx_dac;
-
-   // Wedge DAC #2 at zero
-   assign TXSYNC_B = 1'b0;
-   assign tx_b = 14'b0;
+   // Route transmitted signal to side A or side B
+   assign tx_a = tx_side ? 14'b0 : tx_dac;
+   assign tx_b = tx_side ? tx_dac : 14'b0;
+   assign TXSYNC_A = tx_side ? 1'b0 : tx_sync;
+   assign TXSYNC_B = tx_side ? tx_sync : 1'b0;
    
    /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
    // Receive Side
-   wire        rx_sample_strobe, rx_strobe;
+   wire        rx_strobe;
    wire [15:0] rx_adc0_i, rx_adc0_q;
    wire [15:0] rx_buf_i, rx_buf_q;
    
    adc_interface adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(enable_rx),
 			       .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
-			       .rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(),.rx_b_b(),
+			       .rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_b),.rx_b_b(rx_b_b),
 			       .rssi_0(),.rssi_1(),.rssi_2(),.rssi_3(),
 			       .ddc0_in_i(rx_adc0_i),.ddc0_in_q(rx_adc0_q),
 			       .ddc1_in_i(),.ddc1_in_q(),
@@ -140,10 +142,9 @@ module usrp_radar_mono
 
    ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
    // Top level application
-
    radar radar_mono ( .clk_i(clk64),.saddr_i(serial_addr),.sdata_i(serial_data),.s_strobe_i(serial_strobe),
-	     .tx_strobe_o(tx_sample_strobe),.tx_dac_i_o(tx_i),.tx_dac_q_o(tx_q),
-	     .rx_strobe_i(rx_sample_strobe),.rx_adc_i_i(rx_adc0_i),.rx_adc_q_i(rx_adc0_q),
+	     .tx_side_o(tx_side),.tx_strobe_o(tx_sample_strobe),.tx_dac_i_o(tx_i),.tx_dac_q_o(tx_q),
+	     .rx_adc_i_i(rx_adc0_i),.rx_adc_q_i(rx_adc0_q),
 	     .rx_strobe_o(rx_strobe),.rx_ech_i_o(rx_buf_i),.rx_ech_q_o(rx_buf_q)
 	   );
    
@@ -152,9 +153,9 @@ module usrp_radar_mono
 
    wire [31:0] capabilities;
    assign capabilities[7]   = 0;  // `TX_CAP_HB;
-   assign capabilities[6:4] = 2;  // `TX_CAP_NCHAN;
+   assign capabilities[6:4] = 1;  // `TX_CAP_NCHAN;
    assign capabilities[3]   = 0;  // `RX_CAP_HB;
-   assign capabilities[2:0] = 2;  // `RX_CAP_NCHAN;
+   assign capabilities[2:0] = 1;  // `RX_CAP_NCHAN;
 
    serial_io serial_io
      ( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI),
@@ -172,8 +173,8 @@ module usrp_radar_mono
        .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
        .enable_tx(enable_tx),.enable_rx(enable_rx),
        .interp_rate(),.decim_rate(),
-       .tx_sample_strobe(),.strobe_interp(), // tx_sample_strobe now generated by radar transmitter module
-       .rx_sample_strobe(rx_sample_strobe),.strobe_decim(),
+       .tx_sample_strobe(),.strobe_interp(),
+       .rx_sample_strobe(),.strobe_decim(),
        .tx_empty(tx_empty),
        .debug_0(),.debug_1(),
        .debug_2(),.debug_3(),
diff --git a/gr-radar-mono/src/python/radar_mono.py b/gr-radar-mono/src/python/radar_mono.py
index b8be6a8e2..50af17c0a 100644
--- a/gr-radar-mono/src/python/radar_mono.py
+++ b/gr-radar-mono/src/python/radar_mono.py
@@ -30,10 +30,12 @@ n2s = eng_notation.num_to_str
 #-----------------------------------------------------------------------
 FR_RADAR_MODE           = usrp.FR_USER_0    # Operational mode
 bmFR_RADAR_MODE_RESET   = 1 << 0	# bit 0: active high reset
-#bmFR_RADAR_MODE_LP     = 1 << 1	# bit 1: enable digital loopback
-#bmFR_RADAR_MODE_DR     = 1 << 2	# bit 2: enable on-board deramping
-#bmFR_RADAR_MODE_MD     = 1 << 3   	# bit 3: enable echo metadata
-#bmFR_RADAR_MODE_CHIRPS = 3 << 4   	# bit 4,5: number of chirp center frequencies
+bmFR_RADAR_TXSIDE       = 1 << 1        # bit 1: use TX side A or B
+#bmFR_RADAR_MODE_LP      = 1 << 2	# bit 2: enable digital loopback
+#bmFR_RADAR_MODE_DR      = 1 << 3	# bit 3: enable on-board deramping
+#bmFR_RADAR_MODE_MD      = 1 << 4   	# bit 4: enable echo metadata
+#bmFR_RADAR_MODE_CHIRPS  = 3 << 5   	# bit 5,6: number of chirp center frequencies
+bmFR_RADAR_DEBUG        = 1 << 7        # bit 7: enable debugging mode
 
 FR_RADAR_TON    = usrp.FR_USER_1	# 16-bit transmitter on time in clocks
 FR_RADAR_TSW    = usrp.FR_USER_2	# 16-bit transmitter switch time in clocks
@@ -46,28 +48,31 @@ FR_RADAR_FINCR  = usrp.FR_USER_7  	# 32-bit FTW increment per transmit clock
 # These are for phase II development
 #FR_RADAR_FREQ1N = usrp.FR_USER_8  # 24-bit N register for chirp #1
 #FR_RADAR_FREQ1R = usrp.FR_USER_9  # 24-bit R register for chirp #1
-#FR_RADAR_FREQ1C = usrp.FR_USER_10 # 24-bit control register for chirp #1
+#FR_RADAR_FREQ1C = usrp.FR_USER_10 # 24-bit C register for chirp #1
 #FR_RADAR_FREQ2N = usrp.FR_USER_11 # 24-bit N register for chirp #2
 #FR_RADAR_FREQ2R = usrp.FR_USER_12 # 24-bit R register for chirp #2
-#FR_RADAR_FREQ2C = usrp.FR_USER_13 # 24-bit control register for chirp #2
+#FR_RADAR_FREQ2C = usrp.FR_USER_13 # 24-bit C register for chirp #2
 #FR_RADAR_FREQ3N = usrp.FR_USER_14 # 24-bit N register for chirp #3
 #FR_RADAR_FREQ3R = usrp.FR_USER_15 # 24-bit R register for chirp #3
-#FR_RADAR_FREQ3C = usrp.FR_USER_16 # 24-bit control register for chirp #3
+#FR_RADAR_FREQ3C = usrp.FR_USER_16 # 24-bit C register for chirp #3
 #FR_RADAR_FREQ4N = usrp.FR_USER_17 # 24-bit N register for chirp #4
 #FR_RADAR_FREQ4R = usrp.FR_USER_18 # 24-bit R register for chirp #4
-#FR_RADAR_FREQ4C = usrp.FR_USER_19 # 24-bit control register for chirp #4
+#FR_RADAR_FREQ4C = usrp.FR_USER_19 # 24-bit C register for chirp #4
 
 #-----------------------------------------------------------------------
 # Transmitter object.  Uses usrp_sink, but only for a handle to the
 # FPGA registers.
 #-----------------------------------------------------------------------
 class radar_tx:
-    def __init__(self, verbose=False, debug=False):
+    def __init__(self, subdev_spec=None, verbose=False, debug=False):
+        self._subdev_spec = subdev_spec
 	self._verbose = verbose
 	self._debug = debug
-
         self._u = usrp.sink_s(fpga_filename='usrp_radar_mono.rbf')
-        self._subdev_spec = (0,0); # FPGA code only implements side A
+
+        if self._subdev_spec == None:
+            self._subdev_spec = usrp.pick_tx_subdevice(self._u)
+
         self._subdev = usrp.selected_subdev(self._u, self._subdev_spec)
 	self._subdev.set_lo_offset(0.0)
 	self._ton_ticks = 0
@@ -77,7 +82,7 @@ class radar_tx:
 	
         if self._verbose:
             print "Using", self._subdev.name(), "for radar transmitter."            
-
+	    
     def set_ton(self, ton):
 	self._ton_ticks = 2*(int(ton*64e6)/2)-1  # Even number, then subtract 1
 	if self._verbose:
@@ -105,8 +110,6 @@ class radar_tx:
 
     def set_amplitude(self, ampl):
 	self._amplitude = int(ampl*9946/100.0) # CORDIC gain correction
-        if self._debug:
-            print "Writing amplitude register with:", hex(self._amplitude)
         self._u._write_fpga_reg(FR_RADAR_AMPL, self._amplitude)
 
     def set_freq(self, center_freq, chirp_width):
@@ -132,41 +135,61 @@ class radar_tx:
     def stop(self):
 	self._subdev.set_enable(False)
 	self._u.stop()
+
+    def subdev_spec(self):
+        return self._subdev_spec
+    
+    def echo_length(self):
+        return self._tlook_ticks+1
+
+    def __del__(self):
+	del self._subdev # Avoid weak reference error
 	
 #-----------------------------------------------------------------------
 # Receiver object.  Uses usrp_source_c to receive echo records.
-# NOT IMPLEMENTED YET
 #-----------------------------------------------------------------------
-"""
-class radar_rx:
-    def __init__(self,gain=None,msgq=None,loopback=False,verbose=False,debug=False):
+class radar_rx():
+    def __init__(self, gain=None, subdev_spec=None, msgq=None, length=None,
+                 verbose=False, debug=False):
         self._gain = gain
+        self._subdev_spec = subdev_spec
         self._msgq = msgq
-	self._loopback = loopback
+        self._length = length
 	self._verbose = verbose
-	self._debug = debug
-		
+        self._debug = debug
+	self._length_set = False
+			
         self._fg = gr.flow_graph()
-        self._u = usrp.source_c(fpga_filename='usrp_radar.rbf')
-	if not self._loopback:
-            self._subdev_spec = (0,0) # FPGA only implements side A
-            self._u.set_mux(usrp.determine_rx_mux_value(self._u, self._subdev_spec))
-            self._subdev = usrp.selected_subdev(self._u, self._subdev_spec)
-            if self._verbose:
-	        print "Using", self._subdev.name(), "for radar receiver."
+        self._u = usrp.source_c(fpga_filename='usrp_radar_mono.rbf')
+        if self._subdev_spec == None:
+            self._subdev_spec = usrp.pick_rx_subdevice(self._u)
+        self._u.set_mux(usrp.determine_rx_mux_value(self._u, self._subdev_spec))
 
-        self.set_gain(self._gain)
+	if self._debug:
+	    self._usrp_sink = gr.file_sink(gr.sizeof_gr_complex, "usrp.dat")
+    	    self._fg.connect(self._u, self._usrp_sink)
+	
+        self._subdev = usrp.selected_subdev(self._u, self._subdev_spec)
+        self.set_gain(gain)
 
-        # need to compute length here
+        if self._verbose:
+            print "Using", self._subdev.name(), "for radar receiver."
+            print "Setting receiver gain to", self._gain
         
+    def set_echo_length(self, length):
+        # Only call once
+	if self._length_set is True:
+	    raise RuntimeError("Can only set echo length once.")
+	self._length = length
         self._vblen = gr.sizeof_gr_complex*self._length
-        if self._debug:
-            print "Generating echo vectors of length", self._length, "byte length", self._vblen
-            
-        self._s2v = gr.stream_to_vector(gr.sizeof_gr_complex, self._length)
+	self._s2v = gr.stream_to_vector(gr.sizeof_gr_complex, self._length)
         self._sink = gr.message_sink(self._vblen, self._msgq, True)
         self._fg.connect(self._u, self._s2v, self._sink)
-        
+	self._length_set = True
+        if self._verbose:
+            print "Receiving echo vectors of length", self._length, \
+                  "(samples)", self._vblen, "(bytes)"
+
     def tune(self, frequency):
         if self._verbose:
             print "Setting receiver frequency to", n2s(frequency)
@@ -176,74 +199,68 @@ class radar_rx:
 
     def set_gain(self, gain):
         self._gain = gain
-	if self._loopback:
-	    return
-	    
-        if self._gain is None:
+        if self._gain == None:
             # if no gain was specified, use the mid-point in dB
             g = self._subdev.gain_range()
             self._gain = float(g[0]+g[1])/2
-        if self._verbose:
-            print "Setting receiver gain to", gain
         self._subdev.set_gain(self._gain)
 
     def start(self):
-        if self._debug:
+        if self._verbose:
             print "Starting receiver flow graph."
         self._fg.start()
 
     def wait(self):
-        if self._debug:
+        if self._verbose:
             print "Waiting for threads..."
         self._fg.wait()
 
     def stop(self):
-        if self._debug:
+        if self._verbose:
             print "Stopping receiver flow graph."
         self._fg.stop()
         self.wait()
-        if self._debug:
+        if self._verbose:
             print "Receiver flow graph stopped."
-"""
 
 class radar:
-    def __init__(self,msgq=None,verbose=False,debug=False):
+    def __init__(self, msgq=None, tx_subdev_spec=None, rx_subdev_spec=None,
+                 gain=None, verbose=False, debug=False):
         self._msgq = msgq
         self._verbose = verbose
         self._debug = debug
 
 	self._mode = 0
-        self._trans = radar_tx(verbose=self._verbose, debug=self._debug)
+        self._trans = radar_tx(subdev_spec=tx_subdev_spec, verbose=self._verbose, debug=self._debug)
+        self._rcvr = radar_rx(gain=gain, msgq=self._msgq, subdev_spec=rx_subdev_spec, 
+			      verbose=self._verbose, debug=self._debug)
 	self.set_reset(True)
-		
+	self.set_tx_board(self._trans.subdev_spec())
+        self.set_debug(self._debug)
+        
     def _write_mode(self):
-        if self._debug:
-            print "Writing mode register with:", hex(self._mode)
         self._trans._u._write_fpga_reg(FR_RADAR_MODE, self._mode)
 
     def set_reset(self, value):
 	if value:
-            if self._debug:
-                print "Asserting reset."
 	    self._mode |= bmFR_RADAR_MODE_RESET
 	else:
-            if self._debug:
-                print "De-asserting reset."
 	    self._mode &= ~bmFR_RADAR_MODE_RESET
 	self._write_mode()
 
-    """
-    def set_loopback(self, value):
+    def set_tx_board(self, tx_subdev_spec):
+	if tx_subdev_spec[0] == 1:
+	    self._mode |= bmFR_RADAR_TXSIDE
+	else:
+	    self._mode &= ~bmFR_RADAR_TXSIDE
+	self._write_mode()
+	
+    def set_debug(self, value):
 	if value:
-            if self._verbose:
-                print "Enabling digital loopback."
-	    self._mode |= bmFR_RADAR_MODE_LP
+	    self._mode |= bmFR_RADAR_DEBUG
 	else:
-            if self._verbose:
-                print "Disabling digital loopback."
-	    self._mode &= ~bmFR_RADAR_MODE_LP
+	    self._mode &= ~bmFR_RADAR_DEBUG
 	self._write_mode()
-    """
     
     def set_ton(self, ton):
 	self._trans.set_ton(ton)
@@ -253,6 +270,7 @@ class radar:
 	
     def set_tlook(self, tlook):
 	self._trans.set_tlook(tlook)
+	self._rcvr.set_echo_length(self._trans.echo_length())
 	
     def set_prf(self, prf):
 	self._trans.set_prf(prf)
@@ -265,12 +283,12 @@ class radar:
         # set receiver center frequency
         
     def start(self):
-	self._trans.start()
 	self.set_reset(False)
+	self._trans.start()
+	self._rcvr.start()
 	
     def stop(self):
-	self.set_reset(True)
 	self._trans.stop()
+	self._rcvr.stop()
+	self.set_reset(True)
 
-    def __del__(self):
-        self.stop()
diff --git a/gr-radar-mono/src/python/usrp_radar_mono.py b/gr-radar-mono/src/python/usrp_radar_mono.py
index c4d5ff4a2..e372ec9f0 100755
--- a/gr-radar-mono/src/python/usrp_radar_mono.py
+++ b/gr-radar-mono/src/python/usrp_radar_mono.py
@@ -31,6 +31,12 @@ n2s = eng_notation.num_to_str
 
 def main():
     parser = OptionParser(option_class=eng_option)
+    parser.add_option("-T", "--tx-subdev-spec", type="subdev", default=None,
+		      help="use transmitter board side A or B (default is first found)")
+    parser.add_option("-R", "--rx-subdev-spec", type="subdev", default=None,
+		      help="use receiver board side A or B (default is first found)")
+    parser.add_option("-g", "--gain", type="eng_float", default=None,
+                      help="set gain in dB (default is midpoint)")
     parser.add_option("-f", "--frequency", type="eng_float", default=0.0,
                       help="set transmitter center frequency to FREQ in Hz, default is %default", metavar="FREQ")
     parser.add_option("-w", "--chirp-width", type="eng_float", default=32e6,
@@ -51,8 +57,6 @@ def main():
                       help="enable debugging output, default is disabled")
 
     # NOT IMPLEMENTED
-    #parser.add_option("-g", "--gain", type="eng_float", default=None,
-    #                  help="set gain in dB (default is midpoint)")
     #parser.add_option("-l", "--loopback", action="store_true", default=False,
     #                  help="enable digital loopback, default is disabled")
     #parser.add_option("-F", "--filename", default=None,
@@ -74,7 +78,9 @@ def main():
     """
         
     msgq = gr.msg_queue()
-    s = radar(msgq=msgq,verbose=options.verbose,debug=options.debug)
+    s = radar(msgq=msgq, tx_subdev_spec=options.tx_subdev_spec,
+              rx_subdev_spec=options.rx_subdev_spec,gain=options.gain,
+	      verbose=options.verbose, debug=options.debug)
 
     s.set_ton(options.ton)
     s.set_tsw(options.tsw)
@@ -85,24 +91,22 @@ def main():
 
     s.start()
 
-    """
-    f = open(options.filename, "wb")
+    #f = open(options.filename, "wb")
     print "Enter CTRL-C to stop."
     try:
-        while (1):
-            msg = msgq.delete_head()
-            if msg.type() == 1:
-                break
-            rec = msg.to_string()
-            if options.debug:
-                print "Received echo vector of length", len(rec)
-		f.write(rec)
+	while 1:
+	    if not msgq.empty_p():
+                msg = msgq.delete_head()
+                if msg.type() == 1:
+                    break
+                echo = msg.to_string()
+                if options.debug:
+                    print "Received echo vector of length", len(echo)
+		#f.write(rec)
 		
     except KeyboardInterrupt:
         pass
-    """
 
-    raw_input("Press enter to stop transmitting.")
     s.stop()
         
 if __name__ == "__main__":