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authorTom Rondeau2011-08-29 21:42:42 -0400
committerTom Rondeau2011-08-29 21:42:42 -0400
commite8f68c3db6b4391ba88d36c42f2ce077a02c0c7b (patch)
tree10dec67c582ec64b2068b812648a9e00274e04d8 /gr-digital/lib/digital_lms_dd_equalizer_cc.h
parent9dc241fc48ac4e286cfd51c3bddde0b9f0f40988 (diff)
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Updating QA code for PLL blocks. Setting gains using new loop bw concept changes the behavior slightly so new values were necessary. By explicitly setting alpha and beta to the previous values still worked, though.
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