Merge branch 'master' into next

* master:
  Fixed WBX RX PLL enable
  Refactor WBX and adf4350 to avoid passing usrp pointer
  Clean up annoying class structure in wbx
  Fixing wbx to use _refclk_freq()
  Typo in error message

7 files changed, 158 insertions, 212 deletions

diff --git a/usrp/host/include/usrp/db_wbxng.h b/usrp/host/include/usrp/db_wbxng.h
index 8611d4787..9a7829278 100644
--- a/usrp/host/include/usrp/db_wbxng.h
+++ b/usrp/host/include/usrp/db_wbxng.h
@@ -30,7 +30,7 @@ class adf4350;
 class wbxng_base : public db_base
 {
 public:
-  wbxng_base(usrp_basic_sptr usrp, int which, int _power_on=0);
+  wbxng_base(usrp_basic_sptr usrp, int which);
   ~wbxng_base();
 
   struct freq_result_t set_freq(double freq);
@@ -40,31 +40,30 @@ public:
   double freq_max();
 
 protected:
-  bool _lock_detect();
+  void _write_spi(std::string data);
+  int _refclk_divisor();
+  bool _get_locked();
   bool _set_pga(float pga_gain);
 
-  int power_on() { return d_power_on; }
-  int power_off() { return 0; }
-
   bool d_first;
   int  d_spi_format;
   int  d_spi_enable;
   int  d_power_on;
   int  d_PD;
 
-  adf4350 *d_common;
+  boost::shared_ptr<adf4350> d_common;
 };
 
 // ----------------------------------------------------------------
 
-class wbxng_base_tx : public wbxng_base
+class db_wbxng_tx : public wbxng_base
 {
 protected:
   void shutdown();
 
 public:
-  wbxng_base_tx(usrp_basic_sptr usrp, int which, int _power_on=0);
-  ~wbxng_base_tx();
+  db_wbxng_tx(usrp_basic_sptr usrp, int which);
+  ~db_wbxng_tx();
 
   float gain_min();
   float gain_max();
@@ -75,36 +74,20 @@ public:
   bool set_gain(float gain);
 };
 
-class wbxng_base_rx : public wbxng_base
+class db_wbxng_rx : public wbxng_base
 {
 protected:
   void shutdown();
   bool _set_attn(float attn);
 
 public:
-  wbxng_base_rx(usrp_basic_sptr usrp, int which, int _power_on=0);
-  ~wbxng_base_rx();
+  db_wbxng_rx(usrp_basic_sptr usrp, int which);
+  ~db_wbxng_rx();
 
   bool set_auto_tr(bool on);
   bool select_rx_antenna(int which_antenna);
   bool select_rx_antenna(const std::string &which_antenna);
   bool set_gain(float gain);
-};
-
-// ----------------------------------------------------------------
-
-class db_wbxng_tx : public wbxng_base_tx
-{
- public:
-  db_wbxng_tx(usrp_basic_sptr usrp, int which);
-  ~db_wbxng_tx();
-};
-
-class db_wbxng_rx : public wbxng_base_rx
-{
-public:
-  db_wbxng_rx(usrp_basic_sptr usrp, int which);
-  ~db_wbxng_rx();
 
   float gain_min();
   float gain_max();
diff --git a/usrp/host/lib/db_base.cc b/usrp/host/lib/db_base.cc
index 1cb463429..b4fb45c51 100644
--- a/usrp/host/lib/db_base.cc
+++ b/usrp/host/lib/db_base.cc
@@ -238,7 +238,7 @@ int
 db_base::_refclk_divisor()
 {
   // Return value to stick in REFCLK_DIVISOR register
-  throw std::runtime_error("_reflck_divisor() called from base class\n");;
+  throw std::runtime_error("_refclk_divisor() called from base class\n");;
 }
 
 bool
diff --git a/usrp/host/lib/db_wbxng.cc b/usrp/host/lib/db_wbxng.cc
index bd836dfe3..89200653e 100644
--- a/usrp/host/lib/db_wbxng.cc
+++ b/usrp/host/lib/db_wbxng.cc
@@ -46,8 +46,8 @@
 #define ATTN_SHIFT	8
 #define ATTN_MASK	(63 << ATTN_SHIFT)
 
-wbxng_base::wbxng_base(usrp_basic_sptr _usrp, int which, int _power_on)
-  : db_base(_usrp, which), d_power_on(_power_on)
+wbxng_base::wbxng_base(usrp_basic_sptr _usrp, int which)
+  : db_base(_usrp, which)
 {
   /*
     @param usrp: instance of usrp.source_c
@@ -67,8 +67,12 @@ wbxng_base::wbxng_base(usrp_basic_sptr _usrp, int which, int _power_on)
 
 wbxng_base::~wbxng_base()
 {
-  if (d_common)
-    delete d_common;
+}
+
+int
+wbxng_base::_refclk_divisor()
+{
+  return 1;
 }
 
 struct freq_result_t
@@ -83,8 +87,19 @@ wbxng_base::set_freq(double freq)
   // clamp freq
   freq_t int_freq = freq_t(std::max(freq_min(), std::min(freq, freq_max())));
 
-  bool ok = d_common->_set_freq(int_freq*2);
-  double freq_result = (double) d_common->_get_freq()/2.0;
+  bool ok = d_common->_set_freq(int_freq*2, _refclk_freq());
+
+  _write_spi(d_common->compute_register(5));
+  _write_spi(d_common->compute_register(4));
+  _write_spi(d_common->compute_register(3));
+  /* load involved registers */
+  _write_spi(d_common->compute_register(2));
+  _write_spi(d_common->compute_register(1));
+  _write_spi(d_common->compute_register(0));
+
+  double freq_result = (double) d_common->_get_freq(_refclk_freq())/2.0;
+
+  //ok &= _get_locked();
   struct freq_result_t args = {ok, freq_result};
 
   /* Wait before reading Lock Detect*/
@@ -144,10 +159,22 @@ wbxng_base::freq_max()
   return (double) d_common->_get_max_freq()/2.0;
 }
 
+bool
+wbxng_base::_get_locked(void)
+{
+    return usrp()->read_io(d_which) & PLL_LOCK_DETECT;
+}
+
+void
+wbxng_base::_write_spi(std::string data)
+{
+    usrp()->_write_spi(0, d_spi_enable, d_spi_format, data);
+}
+
 // ----------------------------------------------------------------
 
-wbxng_base_tx::wbxng_base_tx(usrp_basic_sptr _usrp, int which, int _power_on)
-  : wbxng_base(_usrp, which, _power_on)
+db_wbxng_tx::db_wbxng_tx(usrp_basic_sptr _usrp, int which)
+  : wbxng_base(_usrp, which)
 {
   /*
     @param usrp: instance of usrp.sink_c
@@ -161,40 +188,48 @@ wbxng_base_tx::wbxng_base_tx(usrp_basic_sptr _usrp, int which, int _power_on)
     d_spi_enable = SPI_ENABLE_TX_B;
   }
 
-  d_common = new adf4350(_usrp, d_which, d_spi_enable);
+  d_common = boost::shared_ptr<adf4350> (new adf4350());
+
+  /* Initialize the registers. */
+  _write_spi(d_common->compute_register(5));
+  _write_spi(d_common->compute_register(4));
+  _write_spi(d_common->compute_register(3));
+  _write_spi(d_common->compute_register(2));
+  _write_spi(d_common->compute_register(1));
+  _write_spi(d_common->compute_register(0));
 
   // power up the transmit side, but don't enable the mixer
-  usrp()->_write_oe(d_which,(RX_TXN|TXMOD_EN|ENABLE_33|ENABLE_5), (RX_TXN|TXMOD_EN|ENABLE_33|ENABLE_5));
-  usrp()->write_io(d_which, (power_on()|RX_TXN|ENABLE_33|ENABLE_5), (RX_TXN|ENABLE_33|ENABLE_5));
+  usrp()->_write_oe(d_which,(PLL_CE|PLL_PDBRF|RX_TXN|TXMOD_EN|ENABLE_33|ENABLE_5), (PLL_CE|PLL_PDBRF|RX_TXN|TXMOD_EN|ENABLE_33|ENABLE_5));
+  usrp()->write_io(d_which, (PLL_CE|RX_TXN|ENABLE_33|ENABLE_5), (PLL_CE|PLL_PDBRF|RX_TXN|ENABLE_33|ENABLE_5));
   //set_lo_offset(4e6);
   
   // Disable VCO/PLL
-  d_common->_enable(true);
+  //d_common->_enable(true);
+  usrp()->write_io(d_which, (PLL_PDBRF), (PLL_PDBRF));
 
-  set_gain((gain_min() + gain_max()) / 2.0);  // initialize gain
+  set_gain(gain_min());  // initialize gain
 }
 
-wbxng_base_tx::~wbxng_base_tx()
+db_wbxng_tx::~db_wbxng_tx()
 {
   shutdown();
 }
 
-
 void
-wbxng_base_tx::shutdown()
+db_wbxng_tx::shutdown()
 {
-  // fprintf(stderr, "wbxng_base_tx::shutdown  d_is_shutdown = %d\n", d_is_shutdown);
+  // fprintf(stderr, "db_wbxng_tx::shutdown  d_is_shutdown = %d\n", d_is_shutdown);
 
   if (!d_is_shutdown){
     d_is_shutdown = true;
     // do whatever there is to do to shutdown
 
     // Disable VCO/PLL
-    d_common->_enable(false);
+    //d_common->_enable(false);
+    usrp()->write_io(d_which, 0, (PLL_PDBRF));
 
     // Power down and leave the T/R switch in the R position
-    usrp()->write_io(d_which, (power_off()|RX_TXN), (RX_TXN|ENABLE_33|ENABLE_5));
-
+    usrp()->write_io(d_which, (RX_TXN), (PLL_CE|PLL_PDBRF|RX_TXN|ENABLE_33|ENABLE_5));
 
     /*
     _write_control(_compute_control_reg());
@@ -205,7 +240,7 @@ wbxng_base_tx::shutdown()
 }
 
 bool
-wbxng_base_tx::set_auto_tr(bool on)
+db_wbxng_tx::set_auto_tr(bool on)
 {
   bool ok = true;
   if(on) {
@@ -222,7 +257,7 @@ wbxng_base_tx::set_auto_tr(bool on)
 }
 
 bool
-wbxng_base_tx::set_enable(bool on)
+db_wbxng_tx::set_enable(bool on)
 {
   /*
     Enable transmitter if on is true
@@ -244,25 +279,25 @@ wbxng_base_tx::set_enable(bool on)
 }
 
 float
-wbxng_base_tx::gain_min()
+db_wbxng_tx::gain_min()
 {
   return 0.0;
 }
 
 float
-wbxng_base_tx::gain_max()
+db_wbxng_tx::gain_max()
 {
   return 25.0;
 }
 
 float
-wbxng_base_tx::gain_db_per_step()
+db_wbxng_tx::gain_db_per_step()
 {
   return gain_max()/(1+(1.4-0.5)*4096/3.3);
 }
 
 bool
-wbxng_base_tx::set_gain(float gain)
+db_wbxng_tx::set_gain(float gain)
 {
   /*
     Set the gain.
@@ -299,8 +334,8 @@ wbxng_base_tx::set_gain(float gain)
 /**************************************************************************/
 
 
-wbxng_base_rx::wbxng_base_rx(usrp_basic_sptr _usrp, int which, int _power_on)
-  : wbxng_base(_usrp, which, _power_on)
+db_wbxng_rx::db_wbxng_rx(usrp_basic_sptr _usrp, int which)
+  : wbxng_base(_usrp, which)
 {
   /*
     @param usrp: instance of usrp.source_c
@@ -314,15 +349,24 @@ wbxng_base_rx::wbxng_base_rx(usrp_basic_sptr _usrp, int which, int _power_on)
     d_spi_enable = SPI_ENABLE_RX_B;
   }
 
-  d_common = new adf4350(_usrp, d_which, d_spi_enable);
-  
-  // Disable VCO/PLL
-  d_common->_enable(true);
+  d_common = boost::shared_ptr<adf4350> (new adf4350());
 
-  usrp()->_write_oe(d_which, (RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5), (RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5));
-  usrp()->write_io(d_which,  (power_on()|RX2_RX1N|RXBB_EN|ENABLE_33|ENABLE_5), (RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5));
+  /* Initialize the registers. */
+  _write_spi(d_common->compute_register(5));
+  _write_spi(d_common->compute_register(4));
+  _write_spi(d_common->compute_register(3));
+  _write_spi(d_common->compute_register(2));
+  _write_spi(d_common->compute_register(1));
+  _write_spi(d_common->compute_register(0));
+  
+  usrp()->_write_oe(d_which, (PLL_CE|PLL_PDBRF|RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5), (PLL_CE|PLL_PDBRF|RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5));
+  usrp()->write_io(d_which,  (PLL_CE|RX2_RX1N|RXBB_EN|ENABLE_33|ENABLE_5), (PLL_CE|PLL_PDBRF|RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5));
   //fprintf(stderr,"Setting WBXNG RXBB on");
 
+  // Enable VCO/PLL
+  //d_common->_enable(true);
+  usrp()->write_io(d_which, (PLL_PDBRF), (PLL_PDBRF));
+
   // set up for RX on TX/RX port
   select_rx_antenna("TX/RX");
 
@@ -331,43 +375,46 @@ wbxng_base_rx::wbxng_base_rx(usrp_basic_sptr _usrp, int which, int _power_on)
   /*
   set_lo_offset(-4e6);
   */
+
+  set_gain(gain_min());  // initialize gain
 }
 
-wbxng_base_rx::~wbxng_base_rx()
+db_wbxng_rx::~db_wbxng_rx()
 {
   shutdown();
 }
 
 void
-wbxng_base_rx::shutdown()
+db_wbxng_rx::shutdown()
 {
-  // fprintf(stderr, "wbxng_base_rx::shutdown  d_is_shutdown = %d\n", d_is_shutdown);
+  // fprintf(stderr, "db_wbxng_rx::shutdown  d_is_shutdown = %d\n", d_is_shutdown);
 
   if (!d_is_shutdown){
     d_is_shutdown = true;
     // do whatever there is to do to shutdown
 
     // Power down VCO/PLL
-    d_common->_enable(false);
+    //d_common->_enable(false);
+    usrp()->write_io(d_which, 0, (PLL_PDBRF));
 
-    // fprintf(stderr, "wbxng_base_rx::shutdown  before _write_control\n");
+    // fprintf(stderr, "db_wbxng_rx::shutdown  before _write_control\n");
     //_write_control(_compute_control_reg());
 
-    // fprintf(stderr, "wbxng_base_rx::shutdown  before _enable_refclk\n");
+    // fprintf(stderr, "db_wbxng_rx::shutdown  before _enable_refclk\n");
     _enable_refclk(false);                       // turn off refclk
 
-    // fprintf(stderr, "wbxng_base_rx::shutdown  before set_auto_tr\n");
+    // fprintf(stderr, "db_wbxng_rx::shutdown  before set_auto_tr\n");
     set_auto_tr(false);
 
     // Power down
-    usrp()->write_io(d_which, power_off(), (RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5));
+    usrp()->write_io(d_which, 0, (PLL_CE|PLL_PDBRF|RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5));
 
-    // fprintf(stderr, "wbxng_base_rx::shutdown  after set_auto_tr\n");
+    // fprintf(stderr, "db_wbxng_rx::shutdown  after set_auto_tr\n");
   }
 }
 
 bool
-wbxng_base_rx::set_auto_tr(bool on)
+db_wbxng_rx::set_auto_tr(bool on)
 {
   bool ok = true;
   if(on) {
@@ -384,7 +431,7 @@ wbxng_base_rx::set_auto_tr(bool on)
 }
 
 bool
-wbxng_base_rx::select_rx_antenna(int which_antenna)
+db_wbxng_rx::select_rx_antenna(int which_antenna)
 {
   /*
     Specify which antenna port to use for reception.
@@ -404,7 +451,7 @@ wbxng_base_rx::select_rx_antenna(int which_antenna)
 }
 
 bool
-wbxng_base_rx::select_rx_antenna(const std::string &which_antenna)
+db_wbxng_rx::select_rx_antenna(const std::string &which_antenna)
 {
   /*
     Specify which antenna port to use for reception.
@@ -426,7 +473,7 @@ wbxng_base_rx::select_rx_antenna(const std::string &which_antenna)
 }
 
 bool
-wbxng_base_rx::set_gain(float gain)
+db_wbxng_rx::set_gain(float gain)
 {
   /*
     Set the gain.
@@ -441,7 +488,6 @@ wbxng_base_rx::set_gain(float gain)
   float pga_gain, agc_gain;
 
   float maxgain = gain_max() - usrp()->pga_max();
-  float mingain = gain_min();
   if(gain > maxgain) {
     pga_gain = gain-maxgain;
     assert(pga_gain <= usrp()->pga_max());
@@ -456,7 +502,7 @@ wbxng_base_rx::set_gain(float gain)
 }
 
 bool
-wbxng_base_rx::_set_attn(float attn)
+db_wbxng_rx::_set_attn(float attn)
 {
   int attn_code = int(floor(attn/0.5));
   unsigned int iobits = (~attn_code) << ATTN_SHIFT;
@@ -464,27 +510,6 @@ wbxng_base_rx::_set_attn(float attn)
   return usrp()->write_io(d_which, iobits, ATTN_MASK);
 }
 
-// ----------------------------------------------------------------
-
-db_wbxng_tx::db_wbxng_tx(usrp_basic_sptr usrp, int which)
-  : wbxng_base_tx(usrp, which)
-{
-}
-
-db_wbxng_tx::~db_wbxng_tx()
-{
-}
-
-db_wbxng_rx::db_wbxng_rx(usrp_basic_sptr usrp, int which)
-  : wbxng_base_rx(usrp, which)
-{
-  set_gain((gain_min() + gain_max()) / 2.0);  // initialize gain
-}
-
-db_wbxng_rx::~db_wbxng_rx()
-{
-}
-
 float
 db_wbxng_rx::gain_min()
 {
@@ -503,7 +528,6 @@ db_wbxng_rx::gain_db_per_step()
   return 0.05;
 }
 
-
 bool
 db_wbxng_rx::i_and_q_swapped()
 {
diff --git a/usrp/host/lib/db_wbxng_adf4350.cc b/usrp/host/lib/db_wbxng_adf4350.cc
index c17e8d670..f1ab63d82 100644
--- a/usrp/host/lib/db_wbxng_adf4350.cc
+++ b/usrp/host/lib/db_wbxng_adf4350.cc
@@ -27,9 +27,7 @@
 #include <stdio.h>
 
 #define FREQ_C(freq) uint64_t(freq)
-#define INPUT_REF_FREQ FREQ_C(64e6)
 #define DIV_ROUND(num, denom) (((num) + ((denom)/2))/(denom))
-#define INPUT_REF_FREQ_2X (2*INPUT_REF_FREQ)                            /* input ref freq with doubler turned on */
 #define MIN_INT_DIV uint16_t(23)                                        /* minimum int divider, prescaler 4/5 only */
 #define MAX_RF_DIV uint8_t(16)                                          /* max rf divider, divides rf output */
 #define MIN_VCO_FREQ FREQ_C(2.2e9)                                      /* minimum vco freq */
@@ -42,95 +40,46 @@
 #define MUX_PIN       (1 << 1)
 #define LD_PIN        (1 << 0)
 
-adf4350::adf4350(usrp_basic_sptr _usrp, int _which, int _spi_enable)
+adf4350::adf4350()
 {
-    /* Initialize the pin directions. */
-
-    d_usrp = _usrp;
-    d_which = _which;
-    d_spi_enable = _spi_enable;
-    d_spi_format = SPI_FMT_MSB | SPI_FMT_HDR_0;
-
-    d_regs = new adf4350_regs(this);
-
-    /* Outputs */
-    d_usrp->_write_oe(d_which, (CE_PIN | PDB_RF_PIN), (CE_PIN | PDB_RF_PIN));
-    d_usrp->write_io(d_which, (CE_PIN), (CE_PIN | PDB_RF_PIN));
-
-    /* Initialize the pin levels. */
-    _enable(true);
-    /* Initialize the registers. */
-    d_regs->_load_register(5);
-    d_regs->_load_register(4);
-    d_regs->_load_register(3);
-    d_regs->_load_register(2);
-    d_regs->_load_register(1);
-    d_regs->_load_register(0);
+    d_regs = new adf4350_regs();
 }
 
 adf4350::~adf4350()
 {
-    d_usrp->write_io(d_which, (0), (CE_PIN | PDB_RF_PIN));
     delete d_regs;
 }
 
-freq_t
-adf4350::_get_max_freq(void)
-{
-    return MAX_FREQ;
-}
-
-freq_t
-adf4350::_get_min_freq(void)
-{
-    return MIN_FREQ;
-}
-
-bool
-adf4350::_get_locked(void)
-{
-    return d_usrp->read_io(d_which) & LD_PIN;
-}
-
-void
-adf4350::_enable(bool enable)
+std::string
+adf4350::compute_register(uint8_t addr)
 {
-    if (enable){ /* chip enable */
-        d_usrp->write_io(d_which, (PDB_RF_PIN), (PDB_RF_PIN));
-    }else{
-        d_usrp->write_io(d_which, 0, (PDB_RF_PIN));
-    }
-}
+    uint32_t data = d_regs->compute_register(addr);
 
-void
-adf4350::_write(uint8_t addr, uint32_t data)
-{
     data |= addr;
 
-    // create str from data here
+    // create std::string from data here
     char s[4];
     s[0] = (char)((data >> 24) & 0xff);
     s[1] = (char)((data >> 16) & 0xff);
     s[2] = (char)((data >>  8) & 0xff);
     s[3] = (char)(data & 0xff);
-    std::string str(s, 4);
-
-    timespec t;
-    t.tv_sec = 0;
-    t.tv_nsec = 5e6;
+    return std::string(s, 4);
+}
 
-    nanosleep(&t, NULL);
-    d_usrp->_write_spi(0, d_spi_enable, d_spi_format, str);
-    nanosleep(&t, NULL);
+freq_t
+adf4350::_get_max_freq(void)
+{
+    return MAX_FREQ;
+}
 
-    //fprintf(stderr, "Wrote to WBXNG SPI address %d with data %8x\n", addr, data);
-    /* pulse latch */
-    //d_usrp->write_io(d_which, 1, LE_PIN);
-    //d_usrp->write_io(d_which, 0, LE_PIN);
+freq_t
+adf4350::_get_min_freq(void)
+{
+    return MIN_FREQ;
 }
 
 bool
-adf4350::_set_freq(freq_t freq)
+adf4350::_set_freq(freq_t freq, freq_t refclock_freq)
 {
     /* Set the frequency by setting int, frac, mod, r, div */
     if (freq > MAX_FREQ || freq < MIN_FREQ) return false;
@@ -147,7 +96,7 @@ adf4350::_set_freq(freq_t freq)
         d_regs->d_divider_select++; //double the divider
     }
     /* Ramp up the R divider until the N divider is at least the minimum. */
-    //d_regs->d_10_bit_r_counter = INPUT_REF_FREQ*MIN_INT_DIV/freq;
+    //d_regs->d_10_bit_r_counter = refclock_freq*MIN_INT_DIV/freq;
     d_regs->d_10_bit_r_counter = 2;
     uint64_t n_mod;
     do{
@@ -155,7 +104,7 @@ adf4350::_set_freq(freq_t freq)
         n_mod = freq;
         n_mod *= d_regs->d_10_bit_r_counter;
         n_mod *= d_regs->d_mod;
-        n_mod /= INPUT_REF_FREQ;
+        n_mod /= refclock_freq;
         /* calculate int and frac */
         d_regs->d_int = n_mod/d_regs->d_mod;
         d_regs->d_frac = (n_mod - (freq_t)d_regs->d_int*d_regs->d_mod) & uint16_t(0xfff);
@@ -169,38 +118,31 @@ adf4350::_set_freq(freq_t freq)
     }while(d_regs->d_int < min_int_div);
     /* calculate the band select so PFD is under 125 KHz */
     d_regs->d_8_bit_band_select_clock_divider_value = \
-        INPUT_REF_FREQ/(FREQ_C(30e3)*d_regs->d_10_bit_r_counter) + 1;
+        refclock_freq/(FREQ_C(30e3)*d_regs->d_10_bit_r_counter) + 1;
     /*
     fprintf(stderr, "Band Selection: Div %u, Freq %lu\n",
         d_regs->d_8_bit_band_select_clock_divider_value,
-        INPUT_REF_FREQ/(d_regs->d_8_bit_band_select_clock_divider_value * d_regs->d_10_bit_r_counter) + 1
+        refclock_freq/(d_regs->d_8_bit_band_select_clock_divider_value * d_regs->d_10_bit_r_counter) + 1
     );
     */
-    d_regs->_load_register(5);
-    d_regs->_load_register(3);
-    d_regs->_load_register(1);
-    /* load involved registers */
-    d_regs->_load_register(2);
-    d_regs->_load_register(4);
-    d_regs->_load_register(0); /* register 0 must be last */
     return true;
 }
 
 freq_t
-adf4350::_get_freq(void)
+adf4350::_get_freq(freq_t refclock_freq)
 {
     /* Calculate the freq from int, frac, mod, ref, r, div:
      *  freq = (int + frac/mod) * (ref/r)
      * Keep precision by doing multiplies first:
      *  freq = (((((((int)*mod) + frac)*ref)/mod)/r)/div)
      */
-    uint64_t temp;
-    temp = d_regs->d_int;
-    temp *= d_regs->d_mod;
-    temp += d_regs->d_frac;
-    temp *= INPUT_REF_FREQ;
-    temp /= d_regs->d_mod;
-    temp /= d_regs->d_10_bit_r_counter;
-    temp /= (1 << d_regs->d_divider_select);
-    return temp;
+    uint64_t freq;
+    freq = d_regs->d_int;
+    freq *= d_regs->d_mod;
+    freq += d_regs->d_frac;
+    freq *= refclock_freq;
+    freq /= d_regs->d_mod;
+    freq /= d_regs->d_10_bit_r_counter;
+    freq /= (1 << d_regs->d_divider_select);
+    return freq;
 }
diff --git a/usrp/host/lib/db_wbxng_adf4350.h b/usrp/host/lib/db_wbxng_adf4350.h
index 2b0783c20..ce8cbf4b1 100644
--- a/usrp/host/lib/db_wbxng_adf4350.h
+++ b/usrp/host/lib/db_wbxng_adf4350.h
@@ -31,22 +31,16 @@ class adf4350_regs;
 class adf4350
 {
 public:
-    adf4350(usrp_basic_sptr _usrp, int _which, int _spi_enable);
+    adf4350();
     ~adf4350();
     void _update();
-    bool _get_locked();
-    void _enable(bool enable);
-    void _write(uint8_t addr, uint32_t data);
-    bool _set_freq(freq_t freq);
-    freq_t _get_freq();
+    std::string compute_register(uint8_t addr);
+    bool _set_freq(freq_t freq, freq_t refclock_freq);
+    freq_t _get_freq(freq_t refclock_freq);
     freq_t _get_max_freq();
     freq_t _get_min_freq();
 
 protected:
-    usrp_basic_sptr d_usrp;
-    int d_which;
-    int d_spi_enable;
-    int d_spi_format;
     adf4350_regs *d_regs;
 };
 
diff --git a/usrp/host/lib/db_wbxng_adf4350_regs.cc b/usrp/host/lib/db_wbxng_adf4350_regs.cc
index 21d77dcce..aa13d50b9 100644
--- a/usrp/host/lib/db_wbxng_adf4350_regs.cc
+++ b/usrp/host/lib/db_wbxng_adf4350_regs.cc
@@ -55,8 +55,7 @@ const uint8_t adf4350_regs::s_output_power = 3;
 /* reg 5 */
 const uint8_t adf4350_regs::s_ld_pin_mode = 1;
 
-adf4350_regs::adf4350_regs(adf4350* _adf4350){
-    d_adf4350 = _adf4350;
+adf4350_regs::adf4350_regs(){
 
     /* reg 0 */
     d_int = uint16_t(100);
@@ -79,10 +78,10 @@ adf4350_regs::~adf4350_regs(void){
 uint32_t
 adf4350_regs::_reg_shift(uint32_t data, uint32_t shift){
         return data << shift;
-    }
+}
 
-void
-adf4350_regs::_load_register(uint8_t addr){
+uint32_t
+adf4350_regs::compute_register(uint8_t addr){
 	uint32_t data;
 	switch (addr){
 		case 0: data = (
@@ -123,8 +122,9 @@ adf4350_regs::_load_register(uint8_t addr){
 			_reg_shift(s_output_power, 3)); break;
 		case 5: data = (
 			_reg_shift(s_ld_pin_mode, 22)); break;
-		default: return;
+		default: return data;
 	}
-	/* write the data out to spi */
-	d_adf4350->_write(addr, data);
+	/* return the data to write out to spi */
+    return data;
 }
+
diff --git a/usrp/host/lib/db_wbxng_adf4350_regs.h b/usrp/host/lib/db_wbxng_adf4350_regs.h
index 0018aa07f..33a548e85 100644
--- a/usrp/host/lib/db_wbxng_adf4350_regs.h
+++ b/usrp/host/lib/db_wbxng_adf4350_regs.h
@@ -29,13 +29,11 @@ class adf4350;
 class adf4350_regs
 {
 public:
-    adf4350_regs(adf4350* _adf4350);
+    adf4350_regs();
     ~adf4350_regs();
 
-    adf4350* d_adf4350;
-
     uint32_t _reg_shift(uint32_t data, uint32_t shift);
-    void _load_register(uint8_t addr);
+    uint32_t compute_register(uint8_t addr);
 
     /* reg 0 */
     uint16_t d_int;
@@ -75,6 +73,11 @@ public:
     static const uint8_t s_output_power;
     /* reg 5 */
     static const uint8_t s_ld_pin_mode;
+
+protected:
+    usrp_basic_sptr d_usrp;
+    int d_spi_enable;
+    int d_spi_format;
 };
 
 #endif /* ADF4350_REGS_H */