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authormatt2007-03-30 21:52:52 +0000
committermatt2007-03-30 21:52:52 +0000
commitbfc18d83b329dff661eac46aea6801ecffd84942 (patch)
tree00b4b882af4a09a505de2b4a72ea954adf1fb6d5
parentd53437a03ff992f1f3f9651248ac8aad94414fac (diff)
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registered to meet timing
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4826 221aa14e-8319-0410-a670-987f0aec2ac5
-rwxr-xr-xusrp/fpga/sdr_lib/cic_decim.v8
1 files changed, 6 insertions, 2 deletions
diff --git a/usrp/fpga/sdr_lib/cic_decim.v b/usrp/fpga/sdr_lib/cic_decim.v
index 6c20416f1..8c44f006d 100755
--- a/usrp/fpga/sdr_lib/cic_decim.v
+++ b/usrp/fpga/sdr_lib/cic_decim.v
@@ -35,7 +35,8 @@ module cic_decim
input [bw-1:0] signal_in;
output [bw-1:0] signal_out;
reg [bw-1:0] signal_out;
-
+ wire [bw-1:0] signal_out_unreg;
+
wire [bw+maxbitgain-1:0] signal_in_ext;
reg [bw+maxbitgain-1:0] integrator [0:N-1];
reg [bw+maxbitgain-1:0] differentiator [0:N-1];
@@ -83,7 +84,10 @@ module cic_decim
wire [bw+maxbitgain-1:0] signal_out_unnorm = pipeline[N-1];
cic_dec_shifter #(bw)
- cic_dec_shifter(rate,signal_out_unnorm,signal_out);
+ cic_dec_shifter(rate,signal_out_unnorm,signal_out_unreg);
+
+ always @(posedge clock)
+ signal_out <= #1 signal_out_unreg;
endmodule // cic_decim