more initial checkins

git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@3294 221aa14e-8319-0410-a670-987f0aec2ac5

42 files changed, 34039 insertions, 0 deletions

diff --git a/usrp-hw/clockfix/clockfix.bom b/usrp-hw/clockfix/clockfix.bom
new file mode 100644
index 000000000..a7491898a
--- /dev/null
+++ b/usrp-hw/clockfix/clockfix.bom
@@ -0,0 +1,16 @@
+.START
+..device	value	footprint	quantity	refdes
+ADP3336	unknown	MSOP8	1	U1
+CAPACITOR	0.1uF	0603	4	C1 C3 C5 C9
+CAPACITOR	1uF	0603	1	C4
+CAPACITOR	220pF	0603	2	C2 C8
+CAPACITOR	470pF	0603	1	C10
+CONNECTOR_2	unknown	CONNECTOR 1 2	1	J1
+INDUCTOR	unknown	1206	2	L1 L2
+POLARIZED_CAPACITOR	4.7uF	1206	2	C6 C7
+RESISTOR	140k	0603	1	R1
+RESISTOR	50	0603	1	R3
+RESISTOR	78.7k	0603	1	R2
+SMA5	unknown	SMA_VERT	1	J2
+VCTCXO	unknown	CTS_OSC	1	X1
+.END
diff --git a/usrp-hw/clockfix/clockfix.net b/usrp-hw/clockfix/clockfix.net
new file mode 100644
index 000000000..06f66821a
--- /dev/null
+++ b/usrp-hw/clockfix/clockfix.net
@@ -0,0 +1,8 @@
+unnamed_net6	C10-2 R2-1 R1-2 U1-5 
+unnamed_net5	U1-6 U1-7 U1-8 C5-1 L2-2 C6-1 
+unnamed_net4	C1-1 J1-1 C2-1 L1-1 
+unnamed_net3	L2-1 C3-1 C4-1 L1-2 
+unnamed_net2	R3-2 J2-1 
+GND	R2-2 U1-4 J1-2 C5-2 C6-2 C3-2 C4-2 C2-2 C1-2 J2-5 J2-4 J2-3 J2-2 C7-2 C8-2 C9-2 X1-2 
+DVDD	C10-1 R1-1 U1-2 U1-3 U1-1 C7-1 C8-1 C9-1 X1-4 X1-1 
+unnamed_net1	R3-1 X1-3 
diff --git a/usrp-hw/clockfix/clockfix.pcb b/usrp-hw/clockfix/clockfix.pcb
new file mode 100644
index 000000000..0ff309b4b
--- /dev/null
+++ b/usrp-hw/clockfix/clockfix.pcb
@@ -0,0 +1,1209 @@
+# release: pcb-bin 1.99q
+# date:    Thu Jun 23 11:37:18 2005
+# user:    matt (Matt Ettus)
+# host:    localhost.localdomain
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+	SymbolLine[1000 3000 2000 3000 800]
+	SymbolLine[0 3000 500 3500 800]
+)
+Symbol['s' 1200]
+(
+	SymbolLine[500 5000 2000 5000 800]
+	SymbolLine[2000 5000 2500 4500 800]
+	SymbolLine[2000 4000 2500 4500 800]
+	SymbolLine[500 4000 2000 4000 800]
+	SymbolLine[0 3500 500 4000 800]
+	SymbolLine[0 3500 500 3000 800]
+	SymbolLine[500 3000 2000 3000 800]
+	SymbolLine[2000 3000 2500 3500 800]
+	SymbolLine[0 4500 500 5000 800]
+)
+Symbol['t' 1000]
+(
+	SymbolLine[500 1000 500 4500 800]
+	SymbolLine[500 4500 1000 5000 800]
+	SymbolLine[0 2500 1000 2500 800]
+)
+Symbol['u' 1200]
+(
+	SymbolLine[0 3000 0 4500 800]
+	SymbolLine[0 4500 500 5000 800]
+	SymbolLine[500 5000 1500 5000 800]
+	SymbolLine[1500 5000 2000 4500 800]
+	SymbolLine[2000 3000 2000 4500 800]
+)
+Symbol['v' 1200]
+(
+	SymbolLine[0 3000 0 4000 800]
+	SymbolLine[0 4000 1000 5000 800]
+	SymbolLine[1000 5000 2000 4000 800]
+	SymbolLine[2000 3000 2000 4000 800]
+)
+Symbol['w' 1200]
+(
+	SymbolLine[0 3000 0 4500 800]
+	SymbolLine[0 4500 500 5000 800]
+	SymbolLine[500 5000 1000 5000 800]
+	SymbolLine[1000 5000 1500 4500 800]
+	SymbolLine[1500 3000 1500 4500 800]
+	SymbolLine[1500 4500 2000 5000 800]
+	SymbolLine[2000 5000 2500 5000 800]
+	SymbolLine[2500 5000 3000 4500 800]
+	SymbolLine[3000 3000 3000 4500 800]
+)
+Symbol['x' 1200]
+(
+	SymbolLine[0 3000 2000 5000 800]
+	SymbolLine[0 5000 2000 3000 800]
+)
+Symbol['y' 1200]
+(
+	SymbolLine[0 3000 0 4500 800]
+	SymbolLine[0 4500 500 5000 800]
+	SymbolLine[2000 3000 2000 6000 800]
+	SymbolLine[1500 6500 2000 6000 800]
+	SymbolLine[500 6500 1500 6500 800]
+	SymbolLine[0 6000 500 6500 800]
+	SymbolLine[500 5000 1500 5000 800]
+	SymbolLine[1500 5000 2000 4500 800]
+)
+Symbol['z' 1200]
+(
+	SymbolLine[0 3000 2000 3000 800]
+	SymbolLine[0 5000 2000 3000 800]
+	SymbolLine[0 5000 2000 5000 800]
+)
+Symbol['{' 1200]
+(
+	SymbolLine[500 1500 1000 1000 800]
+	SymbolLine[500 1500 500 2500 800]
+	SymbolLine[0 3000 500 2500 800]
+	SymbolLine[0 3000 500 3500 800]
+	SymbolLine[500 3500 500 4500 800]
+	SymbolLine[500 4500 1000 5000 800]
+)
+Symbol['|' 1200]
+(
+	SymbolLine[0 1000 0 5000 800]
+)
+Symbol['}' 1200]
+(
+	SymbolLine[0 1000 500 1500 800]
+	SymbolLine[500 1500 500 2500 800]
+	SymbolLine[500 2500 1000 3000 800]
+	SymbolLine[500 3500 1000 3000 800]
+	SymbolLine[500 3500 500 4500 800]
+	SymbolLine[0 5000 500 4500 800]
+)
+Symbol['~' 1200]
+(
+	SymbolLine[0 3500 500 3000 800]
+	SymbolLine[500 3000 1000 3000 800]
+	SymbolLine[1000 3000 1500 3500 800]
+	SymbolLine[1500 3500 2000 3500 800]
+	SymbolLine[2000 3500 2500 3000 800]
+)
+Via[94000 3000 6000 2000 0 3500 "" "thermal(0)"]
+Via[103000 6000 6000 2000 0 3500 "" "thermal(0)"]
+Via[105000 40000 6000 2000 0 3500 "" "thermal(0)"]
+Via[118000 45000 6000 2000 0 3500 "" "thermal(0)"]
+Via[94000 14000 5999 1998 0 3500 "" "thermal(0)"]
+Via[83000 36000 5999 1996 0 3500 "" "thermal(0)"]
+Via[61000 42000 5999 1996 0 3500 "" "thermal(0)"]
+Via[23000 41000 5999 1996 0 3500 "" "thermal(0)"]
+Via[41000 41000 5999 1996 0 3500 "" "thermal(0)"]
+
+Element["" "0603" "C10" "470pF" 85000 9000 -14000 -2000 0 100 ""]
+(
+	Pad[2400 -900 2400 900 2400 2000 3000 "1" "1" "square"]
+	Pad[-2400 -900 -2400 900 2400 2000 3000 "2" "2" "square"]
+	ElementLine [4200 -2700 4200 2700 600]
+	ElementLine [-4200 -2700 4200 -2700 600]
+	ElementLine [-4200 -2700 -4200 2700 600]
+	ElementLine [-4200 2700 4200 2700 600]
+
+	)
+
+Element["" "0603" "R2" "78.7k" 85000 3000 -13000 -2000 0 100 ""]
+(
+	Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" "square"]
+	Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" "square"]
+	ElementLine [-4200 -2700 -4200 2700 600]
+	ElementLine [-4200 2700 4200 2700 600]
+	ElementLine [4200 -2700 4200 2700 600]
+	ElementLine [-4200 -2700 4200 -2700 600]
+
+	)
+
+Element["" "0603" "R1" "140k" 85000 15000 5000 -3000 0 100 ""]
+(
+	Pad[2400 -900 2400 900 2400 2000 3000 "1" "1" "square"]
+	Pad[-2400 -900 -2400 900 2400 2000 3000 "2" "2" "square"]
+	ElementLine [4200 -2700 4200 2700 600]
+	ElementLine [-4200 -2700 4200 -2700 600]
+	ElementLine [-4200 -2700 -4200 2700 600]
+	ElementLine [-4200 2700 4200 2700 600]
+
+	)
+
+Element["" "1206" "C7" "4.7uF" 103000 17000 -3000 -15000 0 100 ""]
+(
+	Pad[-1800 4800 1800 4800 4800 2000 5400 "1" "1" "square"]
+	Pad[-1800 -4800 1800 -4800 4800 2000 5400 "2" "2" "square"]
+	ElementLine [-5400 8400 5400 8400 1000]
+	ElementLine [5400 -8400 5400 8400 1000]
+	ElementLine [-5400 -8400 5400 -8400 1000]
+	ElementLine [-5400 -8400 -5400 8400 1000]
+
+	)
+
+Element["" "0603" "C5" "0.1uF" 57000 33000 -4000 5000 0 100 ""]
+(
+	Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "square"]
+	Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "square"]
+	ElementLine [-2700 -4200 2700 -4200 600]
+	ElementLine [-2700 -4200 -2700 4200 600]
+	ElementLine [-2700 4200 2700 4200 600]
+	ElementLine [2700 -4200 2700 4200 600]
+
+	)
+
+Element["" "1206" "L2" "unknown" 50000 22000 -3000 -12000 0 100 ""]
+(
+	Pad[-4800 -1800 -4800 1800 4800 2000 5400 "1" "1" "square"]
+	Pad[4800 -1800 4800 1800 4800 2000 5400 "2" "2" "square"]
+	ElementLine [-8400 -5400 -8400 5400 1000]
+	ElementLine [-8400 5400 8400 5400 1000]
+	ElementLine [8400 5400 8400 -5400 1000]
+	ElementLine [8400 -5400 -8400 -5400 1000]
+
+	)
+
+Element["" "0603" "C4" "1uF" 45000 33000 -3000 5000 0 100 ""]
+(
+	Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "square"]
+	Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "square"]
+	ElementLine [-2700 -4200 2700 -4200 600]
+	ElementLine [-2700 -4200 -2700 4200 600]
+	ElementLine [-2700 4200 2700 4200 600]
+	ElementLine [2700 -4200 2700 4200 600]
+
+	)
+
+Element["" "0603" "C3" "0.1uF" 38000 33000 -4000 5000 0 100 ""]
+(
+	Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "square"]
+	Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "square"]
+	ElementLine [-2700 -4200 2700 -4200 600]
+	ElementLine [-2700 -4200 -2700 4200 600]
+	ElementLine [-2700 4200 2700 4200 600]
+	ElementLine [2700 -4200 2700 4200 600]
+
+	)
+
+Element["" "CONNECTOR-1-2" "J1" "unknown" 10000 25000 -3000 -12000 0 100 ""]
+(
+	Pin[0 0 8500 3000 9100 5500 "1" "1" "square"]
+	Pin[0 10000 8500 3000 9100 5500 "2" "2" "thermal(0)"]
+	ElementLine [-5000 -5000 5000 -5000 2000]
+	ElementLine [-5000 -5000 -5000 15000 2000]
+	ElementLine [-5000 15000 5000 15000 2000]
+	ElementLine [5000 -5000 5000 15000 2000]
+	ElementLine [-5000 -5000 -5000 5000 1000]
+	ElementLine [-5000 5000 5000 5000 1000]
+
+	)
+
+Element["" "MSOP8" "U1" "unknown" 93000 28000 -18000 2000 0 100 ""]
+(
+	Pad[-700 0 1500 0 1600 3000 2200 "1" "1" "edge2"]
+	Pad[-700 -2600 1500 -2600 1600 3000 2200 "2" "2" "square,edge2"]
+	Pad[-700 -5100 1500 -5100 1600 3000 2200 "3" "3" "square,edge2"]
+	Pad[-700 -7700 1500 -7700 1600 3000 2200 "4" "4" "square,edge2"]
+	Pad[-17400 -7800 -15200 -7800 1600 3000 2200 "5" "5" "square"]
+	Pad[-17400 -5200 -15200 -5200 1600 3000 2200 "6" "6" "square"]
+	Pad[-17400 -2700 -15200 -2700 1600 3000 2200 "7" "7" "square"]
+	Pad[-17400 -100 -15200 -100 1600 3000 2200 "8" "8" "square"]
+	ElementLine [-9100 1200 2300 1200 1000]
+	ElementLine [-18200 1200 -6700 1200 1000]
+	ElementLine [-18200 -9000 -18200 1200 1000]
+	ElementLine [-18200 -9000 2300 -9000 1000]
+	ElementLine [2300 -9000 2300 1200 1000]
+	ElementArc [-7900 1200 1200 1200 180 180 1000]
+
+	)
+
+Element["" "1206" "C6" "4.7uF" 67000 30000 -3000 -15000 0 100 ""]
+(
+	Pad[-1800 -4800 1800 -4800 4800 2000 5400 "1" "1" "square"]
+	Pad[-1800 4800 1800 4800 4800 2000 5400 "2" "2" "square"]
+	ElementLine [-5400 -8400 5400 -8400 1000]
+	ElementLine [-5400 -8400 -5400 8400 1000]
+	ElementLine [-5400 8400 5400 8400 1000]
+	ElementLine [5400 -8400 5400 8400 1000]
+
+	)
+
+Element["" "0603" "C2" "220pF" 26000 32000 -3000 5000 0 100 ""]
+(
+	Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "square"]
+	Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "square"]
+	ElementLine [-2700 -4200 2700 -4200 600]
+	ElementLine [-2700 -4200 -2700 4200 600]
+	ElementLine [-2700 4200 2700 4200 600]
+	ElementLine [2700 -4200 2700 4200 600]
+
+	)
+
+Element["" "0603" "C1" "0.1uF" 20000 32000 -3000 5000 0 100 ""]
+(
+	Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "square"]
+	Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "square"]
+	ElementLine [-2700 -4200 2700 -4200 600]
+	ElementLine [-2700 -4200 -2700 4200 600]
+	ElementLine [-2700 4200 2700 4200 600]
+	ElementLine [2700 -4200 2700 4200 600]
+
+	)
+
+Element["" "1206" "L1" "unknown" 32000 22000 -3000 -12000 0 100 ""]
+(
+	Pad[-4800 -1800 -4800 1800 4800 2000 5400 "1" "1" "square"]
+	Pad[4800 -1800 4800 1800 4800 2000 5400 "2" "2" "square"]
+	ElementLine [-8400 -5400 -8400 5400 1000]
+	ElementLine [-8400 5400 8400 5400 1000]
+	ElementLine [8400 -5400 8400 5400 1000]
+	ElementLine [-8400 -5400 8400 -5400 1000]
+
+	)
+
+Element["" "0603" "R3" "50" 147000 33000 -3000 -10000 0 100 ""]
+(
+	Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" "square"]
+	Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" "square"]
+	ElementLine [-4200 -2700 -4200 2700 600]
+	ElementLine [-4200 2700 4200 2700 600]
+	ElementLine [4200 2700 4200 -2700 600]
+	ElementLine [4200 -2700 -4200 -2700 600]
+
+	)
+
+Element["" "SMA_VERT" "J2" "unknown" 170000 27000 -4000 -23000 0 100 ""]
+(
+	Pin[0 0 9500 3000 10100 6500 "1" "1" ""]
+	Pin[-10000 10000 9500 3000 10100 6500 "2" "2" "thermal(0)"]
+	Pin[-10000 -10000 9500 3000 10100 6500 "3" "3" "thermal(0)"]
+	Pin[10000 10000 9500 3000 10100 6500 "4" "4" "thermal(0)"]
+	Pin[10000 -10000 9500 3000 10100 6500 "5" "5" "thermal(0)"]
+	ElementLine [-16000 -16000 16000 -16000 1000]
+	ElementLine [16000 -16000 16000 16000 1000]
+	ElementLine [16000 16000 -16000 16000 1000]
+	ElementLine [-16000 16000 -16000 -16000 1000]
+
+	)
+
+Element["" "0603" "C8" "220pF" 91000 34000 5000 3000 1 100 ""]
+(
+	Pad[2400 -900 2400 900 2400 2000 3000 "1" "1" "square"]
+	Pad[-2400 -900 -2400 900 2400 2000 3000 "2" "2" "square"]
+	ElementLine [4200 -2700 4200 2700 600]
+	ElementLine [-4200 -2700 4200 -2700 600]
+	ElementLine [-4200 -2700 -4200 2700 600]
+	ElementLine [-4200 2700 4200 2700 600]
+
+	)
+
+Element["" "0603" "C9" "0.1uF" 107000 31000 -4000 5000 0 100 ""]
+(
+	Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "square"]
+	Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "square"]
+	ElementLine [2700 -4200 2700 4200 600]
+	ElementLine [-2700 4200 2700 4200 600]
+	ElementLine [-2700 -4200 -2700 4200 600]
+	ElementLine [-2700 -4200 2700 -4200 600]
+
+	)
+
+Element["" "CTS_OSC" "X1" "unknown" 118000 17000 5000 -12000 0 100 ""]
+(
+	Pad[15190 -20 17190 -20 7100 1596 8696 "" "4" "square,edge2"]
+	Pad[15190 19980 17190 19980 7100 1596 8696 "" "3" "square,edge2"]
+	Pad[-1310 -20 690 -20 7100 1596 8696 "" "1" "square"]
+	Pad[-1310 19980 690 19980 7100 1596 8696 "" "2" "square"]
+	ElementLine [7400 -2880 10370 -5850 699]
+	ElementLine [4300 -5980 7400 -2880 699]
+	ElementLine [4300 -6010 4300 -5980 699]
+	ElementLine [-7310 25980 23190 25980 699]
+	ElementLine [-7310 -6020 -7310 25980 699]
+	ElementLine [-7310 -6020 23190 -6020 699]
+	ElementLine [23190 -6020 23190 25980 699]
+
+	)
+Layer(1 "solder")
+(
+	Polygon("clearpoly")
+	(
+		[0 0] [190000 0] [190000 50000] [0 50000] 
+	)
+)
+Layer(2 "GND-sldr")
+(
+)
+Layer(3 "Vcc-sldr")
+(
+)
+Layer(4 "component")
+(
+	Line[10000 25000 27000 25000 3000 2000 ""]
+	Line[19100 29600 20000 28700 4000 2000 ""]
+	Line[20000 28700 20000 25000 3000 2000 ""]
+	Line[26900 29600 26000 28700 4000 2000 ""]
+	Line[26000 28700 26000 25000 3000 2000 ""]
+	Line[36800 20200 38600 22000 4000 2000 ""]
+	Line[38600 22000 45000 22000 3000 2000 ""]
+	Line[37100 30600 38000 29700 3000 2000 ""]
+	Line[38000 29700 38000 25000 4000 2000 ""]
+	Line[44100 30600 45000 29700 3000 2000 ""]
+	Line[45000 29700 45000 25000 3000 2000 ""]
+	Line[54800 23800 56000 25000 3000 2000 ""]
+	Line[56000 25000 65000 25000 3000 2000 ""]
+	Line[56100 30600 59000 27700 3000 2000 ""]
+	Line[59000 27700 59000 26000 3000 2000 ""]
+	Line[68800 25200 70000 24000 3000 2000 ""]
+	Line[70000 24000 77000 24000 3000 2000 ""]
+	Line[77000 24000 77000 28000 3000 2000 ""]
+	Line[133190 16980 133170 17000 4000 2000 ""]
+	Line[133170 17000 117000 17000 3000 2000 ""]
+	Line[149400 32100 154500 27000 3000 2000 ""]
+	Line[154500 27000 170000 27000 3000 2000 ""]
+	Line[144600 32100 138700 38000 3000 2000 ""]
+	Line[138700 38000 134000 38000 4000 2000 ""]
+	Line[104800 21800 108600 18000 3000 2000 ""]
+	Line[108600 18000 117000 18000 3000 2000 ""]
+	Line[107900 28600 117000 19500 3000 2000 ""]
+	Line[117000 19500 117000 18000 4000 2000 ""]
+	Line[106100 28600 101000 23500 3000 2000 ""]
+	Line[101000 23500 101000 23000 3000 2000 ""]
+	Line[92300 22900 92400 23000 800 2000 ""]
+	Line[92400 23000 100000 23000 1300 2000 ""]
+	Line[92300 22900 92000 23200 800 2000 ""]
+	Line[92000 23200 92000 28000 1300 2000 ""]
+	Line[93400 33100 93000 32700 800 2000 ""]
+	Line[93000 32700 93000 28000 1300 2000 ""]
+	Line[106100 33400 106000 33500 3000 2000 ""]
+	Line[106000 33500 106000 39000 3000 2000 ""]
+	Line[116690 36980 118000 38290 4000 2000 ""]
+	Line[118000 38290 118000 44000 4000 2000 ""]
+	Line[101200 12200 102000 11400 4000 2000 ""]
+	Line[102000 11400 102000 6000 4000 2000 ""]
+	Line[87400 2100 88300 3000 3000 2000 ""]
+	Line[88300 3000 93000 3000 4000 2000 ""]
+	Line[75600 20200 80800 15000 1800 2000 ""]
+	Line[80800 15000 81000 15300 800 2000 ""]
+	Line[82000 14000 82000 4300 3000 2000 ""]
+	Line[87400 8100 88000 8700 2999 1998 ""]
+	Line[88000 8700 88000 21000 2999 1998 ""]
+	Line[88000 21000 92000 25000 2999 1998 ""]
+	Line[94000 14000 94000 20000 2499 1996 ""]
+	Line[88600 33100 85700 36000 2499 1996 ""]
+	Line[85700 36000 83000 36000 2499 1996 ""]
+	Line[61000 42000 66000 37000 2499 1996 ""]
+	Line[66000 37000 66000 35000 2499 1996 ""]
+	Line[25100 34400 24500 35000 2499 1996 ""]
+	Line[24500 35000 10000 35000 2499 1996 ""]
+	Line[37100 35400 41000 39300 2499 1996 ""]
+	Line[41000 39300 41000 41000 2499 1996 ""]
+	Line[44100 35400 42000 37500 2499 1996 ""]
+	Line[42000 37500 42000 42000 2499 1996 ""]
+	Line[41000 41000 42000 42000 2499 1996 ""]
+	Line[56100 35400 60000 39300 2499 1996 ""]
+	Line[60000 39300 60000 42000 2499 1996 ""]
+	Line[25100 34400 23000 36500 2500 2000 ""]
+	Line[23000 36500 23000 41000 2500 2000 ""]
+	Line[19100 34400 23000 38300 2500 2000 ""]
+	Line[23000 38300 23000 41000 2500 2000 ""]
+)
+Layer(5 "GND-comp")
+(
+)
+Layer(6 "Vcc-comp")
+(
+)
+Layer(7 "unused")
+(
+)
+Layer(8 "unused")
+(
+)
+Layer(9 "silk")
+(
+)
+Layer(10 "silk")
+(
+)
+NetList()
+(
+	Net("unnamed_net6" "(unknown)")
+	(
+		Connect("C10-2")
+		Connect("R2-1")
+		Connect("R1-2")
+		Connect("U1-5")
+	)
+	Net("unnamed_net5" "(unknown)")
+	(
+		Connect("U1-6")
+		Connect("U1-7")
+		Connect("U1-8")
+		Connect("C5-1")
+		Connect("L2-2")
+		Connect("C6-1")
+	)
+	Net("unnamed_net4" "(unknown)")
+	(
+		Connect("C1-1")
+		Connect("J1-1")
+		Connect("C2-1")
+		Connect("L1-1")
+	)
+	Net("unnamed_net3" "(unknown)")
+	(
+		Connect("L2-1")
+		Connect("C3-1")
+		Connect("C4-1")
+		Connect("L1-2")
+	)
+	Net("unnamed_net2" "(unknown)")
+	(
+		Connect("R3-2")
+		Connect("J2-1")
+	)
+	Net("GND" "(unknown)")
+	(
+		Connect("R2-2")
+		Connect("U1-4")
+		Connect("J1-2")
+		Connect("C5-2")
+		Connect("C6-2")
+		Connect("C3-2")
+		Connect("C4-2")
+		Connect("C2-2")
+		Connect("C1-2")
+		Connect("J2-5")
+		Connect("J2-4")
+		Connect("J2-3")
+		Connect("J2-2")
+		Connect("C7-2")
+		Connect("C8-2")
+		Connect("C9-2")
+		Connect("X1-2")
+	)
+	Net("DVDD" "(unknown)")
+	(
+		Connect("C10-1")
+		Connect("R1-1")
+		Connect("U1-2")
+		Connect("U1-3")
+		Connect("U1-1")
+		Connect("C7-1")
+		Connect("C8-1")
+		Connect("C9-1")
+		Connect("X1-4")
+		Connect("X1-1")
+	)
+	Net("unnamed_net1" "(unknown)")
+	(
+		Connect("R3-1")
+		Connect("X1-3")
+	)
+)
diff --git a/usrp-hw/clockfix/clockfix.prj b/usrp-hw/clockfix/clockfix.prj
new file mode 100644
index 000000000..787910056
--- /dev/null
+++ b/usrp-hw/clockfix/clockfix.prj
@@ -0,0 +1,6 @@
+# List all schematics
+schematics clockfix.sch
+
+output-name clockfix
+
+elements-dir ../pkg/newlib
diff --git a/usrp-hw/clockfix/clockfix.sch b/usrp-hw/clockfix/clockfix.sch
new file mode 100644
index 000000000..fc0709bf7
--- /dev/null
+++ b/usrp-hw/clockfix/clockfix.sch
@@ -0,0 +1,333 @@
+v 20040111 1
+C 8200 23400 1 0 0 vctcxo.sym
+{
+T 59600 53500 5 10 1 1 0 6 1
+refdes=X1
+T 59300 52600 5 10 0 1 0 0 1
+footprint=CTS_OSC
+}
+C 57100 53600 1 0 0 generic-power.sym
+{
+T 57300 53850 5 10 1 1 0 3 1
+net=DVDD:1
+}
+C 57200 51600 1 0 0 gnd-1.sym
+C 57100 53300 1 270 0 capacitor-1.sym
+{
+T 56800 52500 5 10 1 1 0 0 1
+refdes=C9
+T 56800 52300 5 10 1 1 0 0 1
+value=0.1uF
+T 57100 53300 5 10 0 1 0 0 1
+footprint=0603
+}
+N 57300 52400 57300 51900 4
+N 57300 53300 57300 53600 4
+N 57300 53500 57700 53500 4
+N 57700 53500 57700 53000 4
+N 57700 53000 57900 53000 4
+N 57300 52100 57700 52100 4
+N 57700 52100 57700 52600 4
+N 57700 52600 57900 52600 4
+C 56300 53300 1 270 0 capacitor-1.sym
+{
+T 56000 52500 5 10 1 1 0 0 1
+refdes=C8
+T 55900 52300 5 10 1 1 0 0 1
+value=220pF
+T 56300 53300 5 10 0 1 0 0 1
+footprint=0603
+}
+N 56500 53500 56500 53300 4
+N 56500 52400 56500 52100 4
+C 60100 52800 1 270 0 generic-power.sym
+{
+T 60350 52600 5 10 1 1 270 3 1
+net=DVDD:1
+}
+N 59900 52600 60100 52600 4
+C 62500 52500 1 0 1 SMA-5.sym
+{
+T 62500 53300 5 10 1 1 0 6 1
+refdes=J2
+T 62500 52500 5 10 0 1 0 0 1
+footprint=SMA_VERT
+}
+C 60700 52900 1 0 0 resistor-1.sym
+{
+T 60900 53200 5 10 1 1 180 8 1
+refdes=R3
+T 60700 52900 5 10 0 1 180 8 1
+footprint=0603
+T 61300 52700 5 10 1 1 0 6 1
+value=50
+}
+N 62000 53000 61600 53000 4
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+N 62400 52300 62400 52500 4
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diff --git a/usrp-hw/clockfix/gnetlistrc b/usrp-hw/clockfix/gnetlistrc
new file mode 100644
index 000000000..6bbd9c292
--- /dev/null
+++ b/usrp-hw/clockfix/gnetlistrc
@@ -0,0 +1,3 @@
+(component-library "../sym")
+(component-library "../sym/generated")
+
diff --git a/usrp-hw/clockfix/gschemrc b/usrp-hw/clockfix/gschemrc
new file mode 100644
index 000000000..6bbd9c292
--- /dev/null
+++ b/usrp-hw/clockfix/gschemrc
@@ -0,0 +1,3 @@
+(component-library "../sym")
+(component-library "../sym/generated")
+
diff --git a/usrp-hw/clockfix/netlist_cmd b/usrp-hw/clockfix/netlist_cmd
new file mode 100755
index 000000000..0196a1261
--- /dev/null
+++ b/usrp-hw/clockfix/netlist_cmd
@@ -0,0 +1,3 @@
+gsch2pcb clockfix.prj
+gnetlist -g partslist3 -o clockfix.bom clockfix.sch
+
diff --git a/usrp-hw/dbsrx/ChangeLog b/usrp-hw/dbsrx/ChangeLog
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/usrp-hw/dbsrx/ChangeLog
diff --git a/usrp-hw/dbsrx/dbsrx.pcb b/usrp-hw/dbsrx/dbsrx.pcb
new file mode 100644
index 000000000..8265a6604
--- /dev/null
+++ b/usrp-hw/dbsrx/dbsrx.pcb
@@ -0,0 +1,3430 @@
+# release: pcb-bin 1.99q
+# date:    Mon Dec 12 15:52:53 2005
+# user:    matt (Matt Ettus)
+# host:    localhost.localdomain
+
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+Cursor[196421 139220 3.195331]
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+Flags(0x0000000000001058)
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+	ElementLine [5000 -5000 5000 15000 2000]
+	ElementLine [-5000 15000 5000 15000 2000]
+	ElementLine [-5000 -5000 -5000 15000 2000]
+	ElementLine [-5000 -5000 5000 -5000 2000]
+
+	)
+
+Element["" "CONNECTOR-8-2" "J25" "unknown" 8000 24000 27700 9900 0 100 ""]
+(
+	Pin[0 0 6000 3000 6600 4000 "1" "1" "square,edge2"]
+	Pin[0 -10000 6000 3000 6600 4000 "2" "2" "edge2,thermal(1)"]
+	Pin[10000 0 6000 3000 6600 4000 "3" "3" "edge2"]
+	Pin[10000 -10000 6000 3000 6600 4000 "4" "4" "edge2,thermal(1)"]
+	Pin[20000 0 6000 3000 6600 4000 "5" "5" "edge2"]
+	Pin[20000 -10000 6000 3000 6600 4000 "6" "6" "edge2,thermal(1)"]
+	Pin[30000 0 6000 3000 6600 4000 "7" "7" "edge2"]
+	Pin[30000 -10000 6000 3000 6600 4000 "8" "8" "edge2,thermal(1)"]
+	Pin[40000 0 6000 3000 6600 4000 "9" "9" "edge2"]
+	Pin[40000 -10000 6000 3000 6600 4000 "10" "10" "edge2,thermal(1)"]
+	Pin[50000 0 6000 3000 6600 4000 "11" "11" "edge2"]
+	Pin[50000 -10000 6000 3000 6600 4000 "12" "12" "edge2,thermal(1)"]
+	Pin[60000 0 6000 3000 6600 4000 "13" "13" "edge2"]
+	Pin[60000 -10000 6000 3000 6600 4000 "14" "14" "edge2,thermal(1)"]
+	Pin[70000 0 6000 3000 6600 4000 "15" "15" "edge2"]
+	Pin[70000 -10000 6000 3000 6600 4000 "16" "16" "edge2,thermal(1)"]
+	ElementLine [-5000 -5000 5000 -5000 1000]
+	ElementLine [5000 -5000 5000 5000 1000]
+	ElementLine [-5000 -15000 -5000 5000 2000]
+	ElementLine [-5000 -15000 75000 -15000 2000]
+	ElementLine [75000 -15000 75000 5000 2000]
+	ElementLine [-5000 5000 75000 5000 2000]
+
+	)
+
+Element["onsolder,lock" "PMC-REVERSE" "J2" "unknown" 94993 95811 -18000 9000 0 100 "auto"]
+(
+	Pin[-6693 7189 7200 2000 7200 5800 "" "1" "hole,lock,edge2"]
+	Pin[128740 7189 7200 2000 7200 5800 "" "2" "hole,lock,edge2"]
+	Pad[0 9900 0 19000 2400 1000 3400 "" "1" "auto,lock,edge2"]
+	Pad[122047 -4622 122047 4478 2400 1000 3400 "" "64" "auto,lock"]
+	Pad[7874 9900 7874 19000 2400 1000 3400 "" "5" "auto,lock,edge2"]
+	Pad[3937 9900 3937 19000 2400 1000 3400 "" "3" "auto,lock,edge2"]
+	Pad[11811 9900 11811 19000 2400 1000 3400 "" "7" "auto,lock,edge2"]
+	Pad[0 -4622 0 4478 2400 1000 3400 "" "2" "auto,lock"]
+	Pad[15748 9900 15748 19000 2400 1000 3400 "" "9" "auto,lock,edge2"]
+	Pad[7874 -4622 7874 4478 2400 1000 3400 "" "6" "auto,lock"]
+	Pad[19685 9900 19685 19000 2400 1000 3400 "" "11" "auto,lock,edge2"]
+	Pad[11811 -4622 11811 4478 2400 1000 3400 "" "8" "auto,lock"]
+	Pad[23622 9900 23622 19000 2400 1000 3400 "" "13" "auto,lock,edge2"]
+	Pad[15748 -4622 15748 4478 2400 1000 3400 "" "10" "auto,lock"]
+	Pad[27559 9900 27559 19000 2400 1000 3400 "" "15" "auto,lock,edge2"]
+	Pad[19685 -4622 19685 4478 2400 1000 3400 "" "12" "auto,lock"]
+	Pad[31496 9900 31496 19000 2400 1000 3400 "" "17" "auto,lock,edge2"]
+	Pad[23622 -4622 23622 4478 2400 1000 3400 "" "14" "auto,lock"]
+	Pad[35433 9900 35433 19000 2400 1000 3400 "" "19" "auto,lock,edge2"]
+	Pad[27559 -4622 27559 4478 2400 1000 3400 "" "16" "auto,lock"]
+	Pad[39370 9900 39370 19000 2400 1000 3400 "" "21" "auto,lock,edge2"]
+	Pad[31496 -4622 31496 4478 2400 1000 3400 "" "18" "auto,lock"]
+	Pad[35433 -4622 35433 4478 2400 1000 3400 "" "20" "auto,lock"]
+	Pad[39370 -4622 39370 4478 2400 1000 3400 "" "22" "auto,lock"]
+	Pad[43307 -4622 43307 4478 2400 1000 3400 "" "24" "auto,lock"]
+	Pad[47244 -4622 47244 4478 2400 1000 3400 "" "26" "auto,lock"]
+	Pad[51181 -4622 51181 4478 2400 1000 3400 "" "28" "auto,lock"]
+	Pad[55118 -4622 55118 4478 2400 1000 3400 "" "30" "auto,lock"]
+	Pad[59055 -4622 59055 4478 2400 1000 3400 "" "32" "auto,lock"]
+	Pad[62992 -4622 62992 4478 2400 1000 3400 "" "34" "auto,lock"]
+	Pad[66929 -4622 66929 4478 2400 1000 3400 "" "36" "auto,lock"]
+	Pad[70866 -4622 70866 4478 2400 1000 3400 "" "38" "auto,lock"]
+	Pad[74803 -4622 74803 4478 2400 1000 3400 "" "40" "auto,lock"]
+	Pad[78740 -4622 78740 4478 2400 1000 3400 "" "42" "auto,lock"]
+	Pad[82677 -4622 82677 4478 2400 1000 3400 "" "44" "auto,lock"]
+	Pad[86614 -4622 86614 4478 2400 1000 3400 "" "46" "auto,lock"]
+	Pad[90551 -4622 90551 4478 2400 1000 3400 "" "48" "auto,lock"]
+	Pad[98425 -4622 98425 4478 2400 1000 3400 "" "52" "auto,lock"]
+	Pad[94488 -4622 94488 4478 2400 1000 3400 "" "50" "auto,lock"]
+	Pad[102362 -4622 102362 4478 2400 1000 3400 "" "54" "auto,lock"]
+	Pad[106299 -4622 106299 4478 2400 1000 3400 "" "56" "auto,lock"]
+	Pad[110236 -4622 110236 4478 2400 1000 3400 "" "58" "auto,lock"]
+	Pad[114173 -4622 114173 4478 2400 1000 3400 "" "60" "auto,lock"]
+	Pad[3937 -4622 3937 4478 2400 1000 3400 "" "4" "auto,lock"]
+	Pad[43307 9900 43307 19000 2400 1000 3400 "" "23" "auto,lock,edge2"]
+	Pad[47244 9900 47244 19000 2400 1000 3400 "" "25" "auto,lock,edge2"]
+	Pad[51181 9900 51181 19000 2400 1000 3400 "" "27" "auto,lock,edge2"]
+	Pad[55118 9900 55118 19000 2400 1000 3400 "" "29" "auto,lock,edge2"]
+	Pad[59055 9900 59055 19000 2400 1000 3400 "" "31" "auto,lock,edge2"]
+	Pad[62992 9900 62992 19000 2400 1000 3400 "" "33" "auto,lock,edge2"]
+	Pad[66929 9900 66929 19000 2400 1000 3400 "" "35" "auto,lock,edge2"]
+	Pad[70866 9900 70866 19000 2400 1000 3400 "" "37" "auto,lock,edge2"]
+	Pad[74803 9900 74803 19000 2400 1000 3400 "" "39" "auto,lock,edge2"]
+	Pad[78740 9900 78740 19000 2400 1000 3400 "" "41" "auto,lock,edge2"]
+	Pad[82677 9900 82677 19000 2400 1000 3400 "" "43" "auto,lock,edge2"]
+	Pad[86614 9900 86614 19000 2400 1000 3400 "" "45" "auto,lock,edge2"]
+	Pad[90551 9900 90551 19000 2400 1000 3400 "" "47" "auto,lock,edge2"]
+	Pad[94488 9900 94488 19000 2400 1000 3400 "" "49" "auto,lock,edge2"]
+	Pad[98425 9900 98425 19000 2400 1000 3400 "" "51" "auto,lock,edge2"]
+	Pad[102362 9900 102362 19000 2400 1000 3400 "" "53" "auto,lock,edge2"]
+	Pad[106299 9900 106299 19000 2400 1000 3400 "" "55" "auto,lock,edge2"]
+	Pad[110236 9900 110236 19000 2400 1000 3400 "" "57" "auto,lock,edge2"]
+	Pad[114173 9900 114173 19000 2400 1000 3400 "" "59" "auto,lock,edge2"]
+	Pad[118110 9900 118110 19000 2400 1000 3400 "" "61" "auto,lock,edge2"]
+	Pad[122047 9900 122047 19000 2400 1000 3400 "" "63" "auto,lock,edge2"]
+	Pad[118110 -4622 118110 4478 2400 1000 3400 "" "62" "auto,lock"]
+	ElementLine [134000 -9000 134000 24000 1000]
+	ElementLine [-11000 24000 134000 24000 1000]
+	ElementLine [-11000 -9000 134000 -9000 1000]
+	ElementLine [-11000 -9000 -11000 24000 1000]
+
+	)
+
+Element["" "0603" "C85" "22pF" 153000 62000 -2700 15500 1 100 ""]
+(
+	Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" "square"]
+	Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" "square"]
+	ElementLine [-2700 -4200 -2700 4200 600]
+	ElementLine [-2700 -4200 2700 -4200 600]
+	ElementLine [2700 -4200 2700 4200 600]
+	ElementLine [-2700 4200 2700 4200 600]
+
+	)
+
+Element["onsolder" "0603" "C25" "100pF" 195500 82500 -4000 -15000 0 100 "auto"]
+(
+	Pad[-2400 -900 -2400 900 2400 3000 2400 "1" "1" "auto,square"]
+	Pad[2400 -900 2400 900 2400 3000 2400 "2" "2" "auto,square"]
+	ElementLine [-4200 2700 4200 2700 600]
+	ElementLine [4200 -2700 4200 2700 600]
+	ElementLine [-4200 -2700 4200 -2700 600]
+	ElementLine [-4200 -2700 -4200 2700 600]
+
+	)
+
+Element["" "0603" "C99" "47pF" 126500 181000 -4500 3800 0 100 ""]
+(
+	Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" "square"]
+	Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" "square"]
+	ElementLine [-4200 -2700 4200 -2700 600]
+	ElementLine [4200 -2700 4200 2700 600]
+	ElementLine [-4200 2700 4200 2700 600]
+	ElementLine [-4200 -2700 -4200 2700 600]
+
+	)
+
+Element["" "SO8" "U6" "unknown" 178500 62000 -2500 10500 0 100 ""]
+(
+	Pad[7000 7500 13500 7500 2000 1000 3000 "1" "1" "square,edge2"]
+	Pad[7000 2500 13500 2500 2000 1000 3000 "2" "2" "square,edge2"]
+	Pad[7000 -2500 13500 -2500 2000 1000 3000 "3" "3" "square,edge2"]
+	Pad[7000 -7500 13500 -7500 2000 1000 3000 "4" "4" "square,edge2"]
+	Pad[-13500 -7500 -7000 -7500 2000 1000 3000 "5" "5" "square"]
+	Pad[-13500 -2500 -7000 -2500 2000 1000 3000 "6" "6" "square"]
+	Pad[-13500 2500 -7000 2500 2000 1000 3000 "7" "7" "square"]
+	Pad[-13500 7500 -7000 7500 2000 1000 3000 "8" "8" "square"]
+	ElementLine [-15500 9500 -2500 9500 1000]
+	ElementLine [2500 9500 15500 9500 1000]
+	ElementLine [-15500 -9500 -15500 9500 1000]
+	ElementLine [-15500 -9500 15500 -9500 1000]
+	ElementLine [15500 -9500 15500 9500 1000]
+	ElementArc [0 9500 2500 2500 180 180 1000]
+
+	)
+
+Element["onsolder" "1206" "L600" "unknown" 104000 133500 -23000 2400 0 100 "auto"]
+(
+	Pad[-4800 -1800 -4800 1800 4800 2000 5400 "1" "1" "auto,square"]
+	Pad[4800 -1800 4800 1800 4800 2000 5400 "2" "2" "auto,square"]
+	ElementLine [-8400 5400 8400 5400 1000]
+	ElementLine [8400 -5400 8400 5400 1000]
+	ElementLine [-8400 -5400 8400 -5400 1000]
+	ElementLine [-8400 -5400 -8400 5400 1000]
+
+	)
+
+Element["" "0603" "R68" "250,_0.1%" 226000 81000 3400 -600 0 100 ""]
+(
+	Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "square"]
+	Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "square"]
+	ElementLine [2700 -4200 2700 4200 600]
+	ElementLine [-2700 4200 2700 4200 600]
+	ElementLine [-2700 -4200 -2700 4200 600]
+	ElementLine [-2700 -4200 2700 -4200 600]
+
+	)
+
+Element["" "0603" "R13" "1K" 201000 201500 -4000 16300 0 100 ""]
+(
+	Pad[2400 -900 2400 900 2400 2000 3000 "1" "1" "square"]
+	Pad[-2400 -900 -2400 900 2400 2000 3000 "2" "2" "square"]
+	ElementLine [-4200 2700 4200 2700 600]
+	ElementLine [-4200 -2700 -4200 2700 600]
+	ElementLine [-4200 -2700 4200 -2700 600]
+	ElementLine [4200 -2700 4200 2700 600]
+
+	)
+
+Element["" "QFN40_6_EP" "U3" "unknown" 193000 174000 -21200 7800 0 100 ""]
+(
+	Pad[-12200 -8800 -10500 -8800 1100 3000 1700 "1" "1" ""]
+	Pad[-12200 -6800 -10500 -6800 1100 3000 1700 "2" "2" ""]
+	Pad[-12200 -4900 -10500 -4900 1100 3000 1700 "3" "3" ""]
+	Pad[-12200 -2900 -10500 -2900 1100 3000 1700 "4" "4" ""]
+	Pad[-12200 -900 -10500 -900 1100 3000 1700 "5" "5" ""]
+	Pad[-12200 900 -10500 900 1100 3000 1700 "6" "6" ""]
+	Pad[-12200 2900 -10500 2900 1100 3000 1700 "7" "7" ""]
+	Pad[-12200 4900 -10500 4900 1100 3000 1700 "8" "8" ""]
+	Pad[-12200 6800 -10500 6800 1100 3000 1700 "9" "9" ""]
+	Pad[-12200 8800 -10500 8800 1100 3000 1700 "10" "10" ""]
+	Pad[-8800 10500 -8800 12200 1100 3000 1700 "11" "11" "edge2"]
+	Pad[-6800 10500 -6800 12200 1100 3000 1700 "12" "12" "edge2"]
+	Pad[-4900 10500 -4900 12200 1100 3000 1700 "13" "13" "edge2"]
+	Pad[-2900 10500 -2900 12200 1100 3000 1700 "14" "14" "edge2"]
+	Pad[-900 10500 -900 12200 1100 3000 1700 "15" "15" "edge2"]
+	Pad[900 10500 900 12200 1100 3000 1700 "16" "16" "edge2"]
+	Pad[2900 10500 2900 12200 1100 3000 1700 "17" "17" "edge2"]
+	Pad[4900 10500 4900 12200 1100 3000 1700 "18" "18" "edge2"]
+	Pad[6800 10500 6800 12200 1100 3000 1700 "19" "19" "edge2"]
+	Pad[8800 10500 8800 12200 1100 3000 1700 "20" "20" "edge2"]
+	Pad[10500 8800 12200 8800 1100 3000 1700 "21" "21" "edge2"]
+	Pad[10500 6800 12200 6800 1100 3000 1700 "22" "22" "edge2"]
+	Pad[10500 4900 12200 4900 1100 3000 1700 "23" "23" "edge2"]
+	Pad[10500 2900 12200 2900 1100 3000 1700 "24" "24" "edge2"]
+	Pad[10500 900 12200 900 1100 3000 1700 "25" "25" "edge2"]
+	Pad[10500 -900 12200 -900 1100 3000 1700 "26" "26" "edge2"]
+	Pad[10500 -2900 12200 -2900 1100 3000 1700 "27" "27" "edge2"]
+	Pad[10500 -4900 12200 -4900 1100 3000 1700 "28" "28" "edge2"]
+	Pad[10500 -6800 12200 -6800 1100 3000 1700 "29" "29" "edge2"]
+	Pad[10500 -8800 12200 -8800 1100 3000 1700 "30" "30" "edge2"]
+	Pad[8800 -12200 8800 -10500 1100 3000 1700 "31" "31" ""]
+	Pad[6800 -12200 6800 -10500 1100 3000 1700 "32" "32" ""]
+	Pad[4900 -12200 4900 -10500 1100 3000 1700 "33" "33" ""]
+	Pad[2900 -12200 2900 -10500 1100 3000 1700 "34" "34" ""]
+	Pad[900 -12200 900 -10500 1100 3000 1700 "35" "35" ""]
+	Pad[-900 -12200 -900 -10500 1100 3000 1700 "36" "36" ""]
+	Pad[-2900 -12200 -2900 -10500 1100 3000 1700 "37" "37" ""]
+	Pad[-4900 -12200 -4900 -10500 1100 3000 1700 "38" "38" ""]
+	Pad[-6800 -12200 -6800 -10500 1100 3000 1700 "39" "39" ""]
+	Pad[-8800 -12200 -8800 -10500 1100 3000 1700 "40" "40" ""]
+	Pad[0 0 0 0 16100 3000 16700 "41" "41" "square,edge2"]
+	ElementLine [-13700 -13700 -15200 -15200 1000]
+	ElementLine [-13700 13700 13700 13700 1000]
+	ElementLine [-13700 -13700 -13700 13700 1000]
+	ElementLine [-13700 -13700 13700 -13700 1000]
+	ElementLine [13700 -13700 13700 13700 1000]
+
+	)
+
+Element["onsolder" "0603" "L100" "27nH" 104000 191500 -16000 8700 0 100 "auto"]
+(
+	Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" "auto,square"]
+	Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" "auto,square"]
+	ElementLine [2700 -4200 2700 4200 600]
+	ElementLine [-2700 -4200 2700 -4200 600]
+	ElementLine [-2700 -4200 -2700 4200 600]
+	ElementLine [-2700 4200 2700 4200 600]
+
+	)
+
+Element["" "0603" "R66" "250,_0.1%" 257000 62000 -1200 15500 1 100 ""]
+(
+	Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "square"]
+	Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "square"]
+	ElementLine [2700 -4200 2700 4200 600]
+	ElementLine [-2700 4200 2700 4200 600]
+	ElementLine [-2700 -4200 -2700 4200 600]
+	ElementLine [-2700 -4200 2700 -4200 600]
+
+	)
+
+Element["" "0603" "R67" "250,_0.1%" 246500 79500 4500 -200 0 100 ""]
+(
+	Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "square"]
+	Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "square"]
+	ElementLine [2700 -4200 2700 4200 600]
+	ElementLine [-2700 4200 2700 4200 600]
+	ElementLine [-2700 -4200 -2700 4200 600]
+	ElementLine [-2700 -4200 2700 -4200 600]
+
+	)
+
+Element["onsolder" "0603" "C100" ".1uF" 111000 201500 -1000 7700 0 100 "auto"]
+(
+	Pad[2400 -900 2400 900 2400 2000 3000 "1" "1" "auto,square"]
+	Pad[-2400 -900 -2400 900 2400 2000 3000 "2" "2" "auto,square"]
+	ElementLine [-4200 -2700 4200 -2700 600]
+	ElementLine [-4200 2700 -4200 -2700 600]
+	ElementLine [-4200 2700 4200 2700 600]
+	ElementLine [4200 2700 4200 -2700 600]
+
+	)
+
+Element["" "0603" "C84" ".1uF" 192000 207500 -5300 16300 0 100 ""]
+(
+	Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" "square"]
+	Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" "square"]
+	ElementLine [-4200 -2700 4200 -2700 600]
+	ElementLine [4200 -2700 4200 2700 600]
+	ElementLine [-4200 2700 4200 2700 600]
+	ElementLine [-4200 -2700 -4200 2700 600]
+
+	)
+
+Element["" "SO8" "U5" "unknown" 236500 62000 -2500 11000 0 100 ""]
+(
+	Pad[7000 7500 13500 7500 2000 1000 3000 "1" "1" "square,edge2"]
+	Pad[7000 2500 13500 2500 2000 1000 3000 "2" "2" "square,edge2"]
+	Pad[7000 -2500 13500 -2500 2000 1000 3000 "3" "3" "square,edge2"]
+	Pad[7000 -7500 13500 -7500 2000 1000 3000 "4" "4" "square,edge2"]
+	Pad[-13500 -7500 -7000 -7500 2000 1000 3000 "5" "5" "square"]
+	Pad[-13500 -2500 -7000 -2500 2000 1000 3000 "6" "6" "square"]
+	Pad[-13500 2500 -7000 2500 2000 1000 3000 "7" "7" "square"]
+	Pad[-13500 7500 -7000 7500 2000 1000 3000 "8" "8" "square"]
+	ElementLine [-15500 9500 -2500 9500 1000]
+	ElementLine [2500 9500 15500 9500 1000]
+	ElementLine [-15500 -9500 -15500 9500 1000]
+	ElementLine [-15500 -9500 15500 -9500 1000]
+	ElementLine [15500 -9500 15500 9500 1000]
+	ElementArc [0 9500 2500 2500 180 180 1000]
+
+	)
+
+Element["" "SC70_6" "U4" "unknown" 134100 175900 400 7600 0 100 ""]
+(
+	Pad[-1000 0 1000 0 1500 3000 2100 "1" "1" "square"]
+	Pad[-1000 2600 1000 2600 1500 3000 2100 "2" "2" "square"]
+	Pad[-1000 5100 1000 5100 1500 3000 2100 "3" "3" "square"]
+	Pad[6000 5100 8000 5100 1500 3000 2100 "4" "4" "square,edge2"]
+	Pad[6000 2600 8000 2600 1500 3000 2100 "5" "5" "square,edge2"]
+	Pad[6000 0 8000 0 1500 3000 2100 "6" "6" "square,edge2"]
+	ElementLine [9400 -1400 9400 6600 1000]
+	ElementLine [-2500 6600 9400 6600 1000]
+	ElementLine [-2500 -1400 -2500 6600 1000]
+	ElementLine [-2500 -1400 9400 -1400 1000]
+
+	)
+
+Element["" "0603" "R14" "2.21K" 201000 207500 -4000 16300 0 100 ""]
+(
+	Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" "square"]
+	Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" "square"]
+	ElementLine [-4200 -2700 4200 -2700 600]
+	ElementLine [4200 -2700 4200 2700 600]
+	ElementLine [-4200 2700 4200 2700 600]
+	ElementLine [-4200 -2700 -4200 2700 600]
+
+	)
+
+Element["onsolder" "0603" "R16" "50" 188000 75000 -4200 -22000 1 100 "auto"]
+(
+	Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "auto,square"]
+	Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "auto,square"]
+	ElementLine [-2700 -4200 -2700 4200 600]
+	ElementLine [-2700 4200 2700 4200 600]
+	ElementLine [2700 -4200 2700 4200 600]
+	ElementLine [-2700 -4200 2700 -4200 600]
+
+	)
+
+Element["" "0603" "C67" "22pF" 264000 62000 300 15000 1 100 ""]
+(
+	Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" "square"]
+	Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" "square"]
+	ElementLine [-2700 -4200 -2700 4200 600]
+	ElementLine [-2700 -4200 2700 -4200 600]
+	ElementLine [2700 -4200 2700 4200 600]
+	ElementLine [-2700 4200 2700 4200 600]
+
+	)
+
+Element["" "0603" "C61" ".1uF" 214900 183500 20600 -2100 0 100 ""]
+(
+	Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" "square"]
+	Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" "square"]
+	ElementLine [-4200 -2700 4200 -2700 600]
+	ElementLine [4200 -2700 4200 2700 600]
+	ElementLine [-4200 2700 4200 2700 600]
+	ElementLine [-4200 -2700 -4200 2700 600]
+
+	)
+
+Element["onsolder" "0603" "C63" ".1uF" 154500 69500 -14000 1200 0 100 "auto"]
+(
+	Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "auto,square"]
+	Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "auto,square"]
+	ElementLine [-2700 4200 -2700 -4200 600]
+	ElementLine [-2700 4200 2700 4200 600]
+	ElementLine [2700 4200 2700 -4200 600]
+	ElementLine [-2700 -4200 2700 -4200 600]
+
+	)
+
+Element["onsolder" "0603" "C65" "100pF" 216000 82500 -2000 -14800 0 100 "auto"]
+(
+	Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" "auto,square"]
+	Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" "auto,square"]
+	ElementLine [-4200 2700 4200 2700 600]
+	ElementLine [4200 -2700 4200 2700 600]
+	ElementLine [-4200 -2700 4200 -2700 600]
+	ElementLine [-4200 -2700 -4200 2700 600]
+
+	)
+
+Element["onsolder" "0603" "R71" "50" 214500 75000 -200 -23500 1 100 "auto"]
+(
+	Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "auto,square"]
+	Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "auto,square"]
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+	)
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+	)
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+	)
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+	)
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+	)
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+	)
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+	)
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+	)
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+	)
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+	Pin[10000 10000 8000 3000 8600 5800 "3" "3" "thermal(1)"]
+	Pin[-10000 -10000 8000 3000 8600 5800 "4" "4" "thermal(1)"]
+	Pin[-10000 10000 8000 3000 8600 5800 "5" "5" "thermal(1)"]
+	ElementLine [16000 -16000 16000 16000 1000]
+	ElementLine [-16000 -16000 16000 -16000 1000]
+	ElementLine [-16000 -16000 -16000 16000 1000]
+	ElementLine [-16000 16000 16000 16000 1000]
+
+	)
+
+Element["" "0603" "C86" "22pF" 204500 62000 -2200 15500 1 100 ""]
+(
+	Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" "square"]
+	Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" "square"]
+	ElementLine [-2700 -4200 -2700 4200 600]
+	ElementLine [-2700 -4200 2700 -4200 600]
+	ElementLine [2700 -4200 2700 4200 600]
+	ElementLine [-2700 4200 2700 4200 600]
+
+	)
+
+Element["" "0603" "R65" "250,_0.1%" 216500 62000 -1700 15500 1 100 ""]
+(
+	Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "square"]
+	Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "square"]
+	ElementLine [2700 -4200 2700 4200 600]
+	ElementLine [-2700 4200 2700 4200 600]
+	ElementLine [-2700 -4200 -2700 4200 600]
+	ElementLine [-2700 -4200 2700 -4200 600]
+
+	)
+
+Element["" "0603" "C66" "22pF" 210500 62000 -1700 15000 1 100 ""]
+(
+	Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" "square"]
+	Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" "square"]
+	ElementLine [-2700 -4200 -2700 4200 600]
+	ElementLine [-2700 -4200 2700 -4200 600]
+	ElementLine [2700 -4200 2700 4200 600]
+	ElementLine [-2700 4200 2700 4200 600]
+
+	)
+
+Element["" "0603" "R18" "250,_0.1%" 198500 62000 -2200 15500 1 100 ""]
+(
+	Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "square"]
+	Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "square"]
+	ElementLine [2700 -4200 2700 4200 600]
+	ElementLine [-2700 4200 2700 4200 600]
+	ElementLine [-2700 -4200 -2700 4200 600]
+	ElementLine [-2700 -4200 2700 -4200 600]
+
+	)
+
+Element["onsolder" "0603" "R193" "10" 154500 78500 -16500 2200 0 100 "auto"]
+(
+	Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" "auto,square"]
+	Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" "auto,square"]
+	ElementLine [2700 -4200 2700 4200 600]
+	ElementLine [-2700 -4200 2700 -4200 600]
+	ElementLine [-2700 -4200 -2700 4200 600]
+	ElementLine [-2700 4200 2700 4200 600]
+
+	)
+
+Element["" "0603" "R22" "NONE" 158000 128500 -14500 -200 0 100 ""]
+(
+	Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" "square"]
+	Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" "square"]
+	ElementLine [-2700 -4200 -2700 4200 600]
+	ElementLine [-2700 -4200 2700 -4200 600]
+	ElementLine [2700 -4200 2700 4200 600]
+	ElementLine [-2700 4200 2700 4200 600]
+
+	)
+
+Element["onsolder" "0603" "R194" "NONE" 160500 68500 0 -6200 2 100 "auto"]
+(
+	Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" "auto,square"]
+	Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" "auto,square"]
+	ElementLine [2700 -4200 2700 4200 600]
+	ElementLine [-2700 -4200 2700 -4200 600]
+	ElementLine [-2700 -4200 -2700 4200 600]
+	ElementLine [-2700 4200 2700 4200 600]
+
+	)
+
+Element["" "CONNECTOR-1-2" "J101" "unknown" 116500 225000 -4000 17000 0 100 ""]
+(
+	Pin[0 0 6000 3000 6600 4000 "1" "1" "square"]
+	Pin[0 10000 6000 3000 6600 4000 "2" "2" ""]
+	ElementLine [-5000 5000 5000 5000 1000]
+	ElementLine [-5000 -5000 -5000 5000 1000]
+	ElementLine [5000 -5000 5000 15000 2000]
+	ElementLine [-5000 15000 5000 15000 2000]
+	ElementLine [-5000 -5000 -5000 15000 2000]
+	ElementLine [-5000 -5000 5000 -5000 2000]
+
+	)
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+	Line[186200 187300 185000 188500 798 1596 "clearline"]
+	Line[110000 161500 110000 175000 3999 1996 ""]
+	Line[110000 175000 128500 175000 3999 1996 ""]
+	Line[128500 175000 130500 173000 3999 1996 ""]
+	Line[130500 173000 130500 161000 3999 1996 ""]
+	Line[130500 161000 110000 161000 3999 1996 ""]
+	Line[110000 161000 110000 162000 3999 1996 ""]
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+	Line[127000 165500 127000 172500 3999 1996 ""]
+	Line[127000 172500 112000 172500 3999 1996 ""]
+	Line[112000 172500 111500 172000 3999 1996 ""]
+	Line[111500 172000 111500 168500 3999 1996 ""]
+	Line[111500 168500 112000 168000 3999 1996 ""]
+	Line[112000 168000 122500 168000 3999 1996 ""]
+	Line[122500 168000 123500 169000 3999 1996 ""]
+	Line[123500 169000 119500 169000 3999 1996 ""]
+	Line[119500 169000 117500 171000 3999 1996 ""]
+	Line[117500 171000 120500 171000 3999 1996 ""]
+	Line[120500 171000 127500 164000 3999 1996 ""]
+	Line[127500 164000 114500 164000 3999 1996 ""]
+	Line[114500 164000 114000 164500 3999 1996 ""]
+	Line[114000 164500 114000 163500 3999 1996 ""]
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+	Line[130000 174500 131000 175500 3999 1996 ""]
+	Line[131000 175500 131500 175500 3999 1996 ""]
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+	Line[132000 176000 132000 173500 3999 1996 ""]
+	Line[132000 173500 131000 172500 3999 1996 ""]
+	Line[134500 186500 156500 186500 3999 1996 ""]
+	Line[156500 186500 156500 203000 3999 1996 ""]
+	Line[156500 203000 134500 203000 3999 1996 ""]
+	Line[134500 203000 134500 190000 3999 1996 ""]
+	Line[134500 190000 153500 190000 3999 1996 ""]
+	Line[153500 190000 153500 200000 3999 1996 ""]
+	Line[153500 200000 137000 200000 3999 1996 ""]
+	Line[137000 200000 137000 194000 3999 1996 ""]
+	Line[137000 194000 137500 193500 3999 1996 ""]
+	Line[137500 193500 151000 193500 3999 1996 ""]
+	Line[151000 193500 151000 196500 3999 1996 ""]
+	Line[151000 196500 139500 196500 3999 1996 ""]
+	Line[139500 196500 134500 191500 3999 1996 ""]
+	Line[134500 191500 134500 186500 3999 1996 ""]
+	Line[134500 186500 137500 186500 3999 1996 ""]
+	Line[137500 186500 141500 182500 3999 1996 ""]
+	Line[141500 182500 150000 182500 3999 1996 ""]
+	Line[150000 182500 151000 183500 3999 1996 ""]
+	Line[151000 183500 151000 184000 3999 1996 ""]
+	Line[151000 184000 151500 184500 3999 1996 ""]
+	Line[151500 184500 153000 184500 3999 1996 ""]
+	Text[210000 4000 0 100 "COMPONENT" ""]
+	Polygon("clearpoly")
+	(
+		[185000 166000] [201000 166000] [201000 182000] [185000 182000] 
+	)
+	Polygon("clearpoly")
+	(
+		[185000 166000] [201000 166000] [201000 182000] [185000 182000] 
+	)
+	Polygon("clearpoly")
+	(
+		[188000 167500] [194500 167500] [194500 177000] [188000 177000] 
+	)
+)
+Layer(5 "OTHER5")
+(
+)
+Layer(6 "OTHER6")
+(
+)
+Layer(7 "OTHER7")
+(
+)
+Layer(8 "OTHER8")
+(
+)
+Layer(9 "silk")
+(
+	Text[210000 18500 0 100 "BACK SILK" "auto"]
+)
+Layer(10 "silk")
+(
+	Text[53000 222500 0 100 "Antenna Bias" ""]
+	Text[102800 46100 1 78 "io_rx[7]" ""]
+	Text[39000 1500 0 100 "GND" ""]
+	Text[39500 234000 0 100 "500mA MAX" ""]
+	Text[90500 221000 0 200 "+" ""]
+	Text[7000 49400 1 78 "io_rx[15]" ""]
+	Text[210000 9500 0 100 "SILK" ""]
+	Text[80000 232000 0 150 "GND" ""]
+	Text[76700 46800 1 78 "io_rx[8]" ""]
+	Text[169100 31100 0 78 "io_rx[0]" ""]
+	Text[132000 2500 0 100 "GND" ""]
+	Text[3500 179500 0 150 "DBSRX" ""]
+	Text[110500 211500 0 150 "6V Bias" ""]
+	Text[3000 191500 0 150 "Rev 2.1" ""]
+	Text[3500 149000 0 150 "800-2400MHz Receiver" ""]
+	Text[132000 169000 0 100 "." ""]
+	Text[3000 204000 0 150 "(c) 2006 Ettus Research LLC" ""]
+)
+NetList()
+(
+	Net("unnamed_net37" "(unknown)")
+	(
+		Connect("C183-2")
+		Connect("L601-1")
+		Connect("L600-2")
+	)
+	Net("unnamed_net36" "(unknown)")
+	(
+		Connect("C184-2")
+		Connect("L601-2")
+		Connect("U2-1")
+	)
+	Net("unnamed_net35" "(unknown)")
+	(
+		Connect("J101-1")
+		Connect("C100-2")
+		Connect("L100-1")
+		Connect("J100-1")
+	)
+	Net("unnamed_net34" "(unknown)")
+	(
+		Connect("C86-1")
+		Connect("R18-2")
+		Connect("R19-1")
+		Connect("U6-1")
+	)
+	Net("unnamed_net33" "(unknown)")
+	(
+		Connect("C85-1")
+		Connect("R17-2")
+		Connect("R20-1")
+		Connect("U6-8")
+	)
+	Net("unnamed_net32" "(unknown)")
+	(
+		Connect("C86-2")
+		Connect("R18-1")
+		Connect("U6-4")
+		Connect("R16-1")
+	)
+	Net("unnamed_net31" "(unknown)")
+	(
+		Connect("C85-2")
+		Connect("R17-1")
+		Connect("U6-5")
+		Connect("R15-1")
+	)
+	Net("unnamed_net30" "(unknown)")
+	(
+		Connect("R14-1")
+		Connect("C84-2")
+	)
+	Net("unnamed_net29" "(unknown)")
+	(
+		Connect("R194-1")
+		Connect("C261-1")
+		Connect("R193-2")
+		Connect("C63-2")
+	)
+	Net("unnamed_net28" "(unknown)")
+	(
+		Connect("R93-1")
+		Connect("C61-2")
+	)
+	Net("unnamed_net27" "(unknown)")
+	(
+		Connect("C73-1")
+		Connect("R11-2")
+	)
+	Net("unnamed_net26" "(unknown)")
+	(
+		Connect("U4-6")
+		Connect("L98-2")
+		Connect("C96-1")
+	)
+	Net("unnamed_net25" "(unknown)")
+	(
+		Connect("U4-3")
+		Connect("C99-2")
+	)
+	Net("unnamed_net24" "(unknown)")
+	(
+		Connect("L100-2")
+		Connect("J3-1")
+		Connect("C99-1")
+	)
+	Net("unnamed_net23" "(unknown)")
+	(
+		Connect("R40-2")
+		Connect("C96-2")
+		Connect("R9-1")
+	)
+	Net("unnamed_net22" "(unknown)")
+	(
+		Connect("C72-1")
+		Connect("R9-2")
+	)
+	Net("unnamed_net21" "(unknown)")
+	(
+		Connect("R19-2")
+		Connect("U3-36")
+	)
+	Net("unnamed_net20" "(unknown)")
+	(
+		Connect("R20-2")
+		Connect("U3-37")
+	)
+	Net("unnamed_net19" "(unknown)")
+	(
+		Connect("R22-1")
+		Connect("R21-1")
+		Connect("C87-2")
+		Connect("U3-7")
+	)
+	Net("unnamed_net18" "(unknown)")
+	(
+		Connect("C73-2")
+		Connect("U3-4")
+	)
+	Net("unnamed_net17" "(unknown)")
+	(
+		Connect("C72-2")
+		Connect("U3-5")
+	)
+	Net("VccVCO" "(unknown)")
+	(
+		Connect("R12-1")
+		Connect("C82-1")
+		Connect("C80-1")
+		Connect("U3-13")
+	)
+	Net("unnamed_net16" "(unknown)")
+	(
+		Connect("C71-1")
+		Connect("U3-20")
+	)
+	Net("unnamed_net15" "(unknown)")
+	(
+		Connect("C70-1")
+		Connect("U3-14")
+	)
+	Net("unnamed_net14" "(unknown)")
+	(
+		Connect("C69-1")
+		Connect("U3-40")
+	)
+	Net("unnamed_net13" "(unknown)")
+	(
+		Connect("C69-2")
+		Connect("U3-39")
+	)
+	Net("unnamed_net12" "(unknown)")
+	(
+		Connect("C68-1")
+		Connect("U3-1")
+	)
+	Net("unnamed_net11" "(unknown)")
+	(
+		Connect("C68-2")
+		Connect("U3-2")
+	)
+	Net("unnamed_net10" "(unknown)")
+	(
+		Connect("C63-1")
+		Connect("C61-1")
+		Connect("U3-21")
+	)
+	Net("unnamed_net9" "(unknown)")
+	(
+		Connect("C83-2")
+		Connect("R14-2")
+		Connect("R13-1")
+		Connect("U3-17")
+	)
+	Net("unnamed_net8" "(unknown)")
+	(
+		Connect("R13-2")
+		Connect("C59-1")
+		Connect("U3-16")
+	)
+	Net("unnamed_net7" "(unknown)")
+	(
+		Connect("Q1-3")
+		Connect("U3-26")
+	)
+	Net("unnamed_net6" "(unknown)")
+	(
+		Connect("U3-34")
+		Connect("R68-2")
+	)
+	Net("unnamed_net5" "(unknown)")
+	(
+		Connect("U3-33")
+		Connect("R67-2")
+	)
+	Net("5V_RF" "(unknown)")
+	(
+		Connect("J101-2")
+		Connect("C182-1")
+		Connect("U2-3")
+		Connect("C28-1")
+		Connect("C27-1")
+		Connect("U6-3")
+		Connect("R12-2")
+		Connect("C81-1")
+		Connect("C79-2")
+		Connect("U3-38")
+		Connect("C78-2")
+		Connect("U3-35")
+		Connect("C77-2")
+		Connect("U3-30")
+		Connect("C76-2")
+		Connect("U3-19")
+		Connect("C75-2")
+		Connect("U3-12")
+		Connect("C74-2")
+		Connect("U3-3")
+		Connect("U5-3")
+	)
+	Net("unnamed_net4" "(unknown)")
+	(
+		Connect("C67-1")
+		Connect("R66-2")
+		Connect("R67-1")
+		Connect("U5-1")
+	)
+	Net("unnamed_net3" "(unknown)")
+	(
+		Connect("C66-1")
+		Connect("R65-2")
+		Connect("R68-1")
+		Connect("U5-8")
+	)
+	Net("unnamed_net2" "(unknown)")
+	(
+		Connect("C67-2")
+		Connect("R66-1")
+		Connect("U5-4")
+		Connect("R71-1")
+	)
+	Net("unnamed_net1" "(unknown)")
+	(
+		Connect("C66-2")
+		Connect("R65-1")
+		Connect("U5-5")
+		Connect("R10-1")
+	)
+	Net("local_vref" "(unknown)")
+	(
+		Connect("U6-2")
+		Connect("U5-2")
+		Connect("C124-1")
+		Connect("C24-1")
+		Connect("R7-1")
+		Connect("R6-2")
+	)
+	Net("AUX_ADC_B1" "(unknown)")
+	(
+		Connect("J2-61")
+	)
+	Net("AUX_ADC_A1" "(unknown)")
+	(
+		Connect("J2-59")
+	)
+	Net("AUX_ADC_REF" "(unknown)")
+	(
+		Connect("J2-57")
+	)
+	Net("AUX_DAC_C" "(unknown)")
+	(
+		Connect("J2-55")
+	)
+	Net("AUX_DAC_B" "(unknown)")
+	(
+		Connect("J2-53")
+	)
+	Net("AUX_DAC_A" "(unknown)")
+	(
+		Connect("R21-2")
+		Connect("J2-51")
+	)
+	Net("AUX_DAC_D" "(unknown)")
+	(
+		Connect("J2-49")
+	)
+	Net("SEN_RX" "(unknown)")
+	(
+		Connect("J2-35")
+	)
+	Net("VINP_A" "(unknown)")
+	(
+		Connect("C65-1")
+		Connect("R71-2")
+		Connect("J2-62")
+	)
+	Net("VINN_A" "(unknown)")
+	(
+		Connect("C64-1")
+		Connect("R10-2")
+		Connect("J2-60")
+	)
+	Net("VREF" "(unknown)")
+	(
+		Connect("J2-56")
+	)
+	Net("VINN_B" "(unknown)")
+	(
+		Connect("C25-1")
+		Connect("R15-2")
+		Connect("J2-52")
+	)
+	Net("VINP_B" "(unknown)")
+	(
+		Connect("C26-1")
+		Connect("R16-2")
+		Connect("J2-50")
+	)
+	Net("AVDD" "(unknown)")
+	(
+		Connect("C97-1")
+		Connect("L98-1")
+		Connect("C98-1")
+		Connect("R6-1")
+		Connect("J2-45")
+		Connect("J2-43")
+		Connect("J2-46")
+		Connect("J2-44")
+	)
+	Net("AGND" "(unknown)")
+	(
+		Connect("R93-2")
+		Connect("U4-1")
+		Connect("U4-2")
+		Connect("U4-5")
+		Connect("U4-4")
+		Connect("C184-1")
+		Connect("C183-1")
+		Connect("C182-2")
+		Connect("U2-4")
+		Connect("U2-2")
+		Connect("C100-1")
+		Connect("J100-2")
+		Connect("Q1-2")
+		Connect("J3-5")
+		Connect("J3-4")
+		Connect("J3-3")
+		Connect("J3-2")
+		Connect("C28-2")
+		Connect("C27-2")
+		Connect("C87-1")
+		Connect("U6-6")
+		Connect("C26-2")
+		Connect("C25-2")
+		Connect("C59-2")
+		Connect("C84-1")
+		Connect("C83-1")
+		Connect("C82-2")
+		Connect("C81-2")
+		Connect("C80-2")
+		Connect("C75-1")
+		Connect("C76-1")
+		Connect("C77-1")
+		Connect("C78-1")
+		Connect("C79-1")
+		Connect("C74-1")
+		Connect("R11-1")
+		Connect("R40-1")
+		Connect("C97-2")
+		Connect("C98-2")
+		Connect("C71-2")
+		Connect("C70-2")
+		Connect("U3-10")
+		Connect("U3-41")
+		Connect("U3-25")
+		Connect("U3-31")
+		Connect("U3-11")
+		Connect("U3-18")
+		Connect("U3-9")
+		Connect("U3-6")
+		Connect("U5-6")
+		Connect("C65-2")
+		Connect("C64-2")
+		Connect("C124-2")
+		Connect("R7-2")
+		Connect("C24-2")
+		Connect("J2-63")
+		Connect("J2-47")
+		Connect("J2-41")
+		Connect("J2-64")
+		Connect("J2-58")
+		Connect("J2-54")
+		Connect("J2-48")
+		Connect("J2-42")
+	)
+	Net("io_rx_00" "(unknown)")
+	(
+		Connect("R193-1")
+		Connect("J2-36")
+	)
+	Net("io_rx_01" "(unknown)")
+	(
+		Connect("J24-13")
+		Connect("J2-34")
+	)
+	Net("io_rx_02" "(unknown)")
+	(
+		Connect("J24-11")
+		Connect("J2-32")
+	)
+	Net("io_rx_03" "(unknown)")
+	(
+		Connect("R22-2")
+		Connect("J24-9")
+		Connect("J2-30")
+	)
+	Net("io_rx_04" "(unknown)")
+	(
+		Connect("J24-7")
+		Connect("J2-28")
+	)
+	Net("SDI" "(unknown)")
+	(
+		Connect("J2-33")
+	)
+	Net("SDO" "(unknown)")
+	(
+		Connect("J2-31")
+	)
+	Net("SCLK" "(unknown)")
+	(
+		Connect("J2-29")
+	)
+	Net("RESET" "(unknown)")
+	(
+		Connect("J2-27")
+	)
+	Net("io_rx_05" "(unknown)")
+	(
+		Connect("J24-5")
+		Connect("J2-26")
+	)
+	Net("RS232_RXD" "(unknown)")
+	(
+		Connect("J2-25")
+	)
+	Net("io_rx_06" "(unknown)")
+	(
+		Connect("J24-3")
+		Connect("J2-24")
+	)
+	Net("RS232_TXD" "(unknown)")
+	(
+		Connect("J2-23")
+	)
+	Net("io_rx_07" "(unknown)")
+	(
+		Connect("J24-1")
+		Connect("J2-22")
+	)
+	Net("I2C_A0" "(unknown)")
+	(
+		Connect("J2-21")
+	)
+	Net("io_rx_08" "(unknown)")
+	(
+		Connect("J25-15")
+		Connect("J2-20")
+	)
+	Net("I2C_A1" "(unknown)")
+	(
+		Connect("Q1-1")
+		Connect("U1-2")
+		Connect("J2-19")
+	)
+	Net("io_rx_09" "(unknown)")
+	(
+		Connect("J25-13")
+		Connect("J2-18")
+	)
+	Net("SDA" "(unknown)")
+	(
+		Connect("U3-27")
+		Connect("U1-5")
+		Connect("J2-17")
+	)
+	Net("io_rx_10" "(unknown)")
+	(
+		Connect("J25-11")
+		Connect("J2-16")
+	)
+	Net("SCL" "(unknown)")
+	(
+		Connect("U3-29")
+		Connect("U1-6")
+		Connect("J2-15")
+	)
+	Net("io_rx_11" "(unknown)")
+	(
+		Connect("J25-9")
+		Connect("J2-14")
+	)
+	Net("io_rx_12" "(unknown)")
+	(
+		Connect("J25-7")
+		Connect("J2-12")
+	)
+	Net("clock_p" "(unknown)")
+	(
+		Connect("R194-2")
+		Connect("J2-11")
+	)
+	Net("io_rx_13" "(unknown)")
+	(
+		Connect("J25-5")
+		Connect("J2-10")
+	)
+	Net("io_rx_14" "(unknown)")
+	(
+		Connect("J25-3")
+		Connect("J2-8")
+	)
+	Net("DVDD" "(unknown)")
+	(
+		Connect("U1-8")
+		Connect("U1-3")
+		Connect("U1-1")
+		Connect("J2-9")
+		Connect("J2-7")
+	)
+	Net("io_rx_15" "(unknown)")
+	(
+		Connect("J25-1")
+		Connect("J2-6")
+	)
+	Net("6V" "(unknown)")
+	(
+		Connect("L600-1")
+		Connect("C187-2")
+		Connect("J2-5")
+		Connect("J2-3")
+	)
+	Net("DGND" "(unknown)")
+	(
+		Connect("C261-2")
+		Connect("C187-1")
+		Connect("J25-6")
+		Connect("J25-4")
+		Connect("J25-14")
+		Connect("J25-12")
+		Connect("J25-10")
+		Connect("J25-16")
+		Connect("J25-8")
+		Connect("J25-2")
+		Connect("J24-6")
+		Connect("J24-4")
+		Connect("J24-14")
+		Connect("J24-12")
+		Connect("J24-10")
+		Connect("J24-16")
+		Connect("J24-8")
+		Connect("J24-2")
+		Connect("U1-4")
+		Connect("U1-7")
+		Connect("J2-37")
+		Connect("J2-38")
+		Connect("J2-2")
+		Connect("J2-1")
+	)
+)
diff --git a/usrp-hw/dbsrx/dbsrx.prj b/usrp-hw/dbsrx/dbsrx.prj
new file mode 100644
index 000000000..cbe51968e
--- /dev/null
+++ b/usrp-hw/dbsrx/dbsrx.prj
@@ -0,0 +1,6 @@
+# List all schematics
+schematics dbsrx.sch
+
+output-name dbsrx
+
+elements-dir ../pkg/newlib
diff --git a/usrp-hw/dbsrx/dbsrx.sch b/usrp-hw/dbsrx/dbsrx.sch
new file mode 100644
index 000000000..32ddb2ccd
--- /dev/null
+++ b/usrp-hw/dbsrx/dbsrx.sch
@@ -0,0 +1,1688 @@
+v 20050820 1
+C 83700 45200 1 180 1 pmc64.sym
+{
+T 84400 32000 5 10 1 1 0 2 1
+refdes=J2
+T 83700 45200 5 10 0 1 90 6 1
+footprint=PMC-REVERSE
+}
+N 85200 40100 86900 40100 4
+{
+T 85500 40100 5 10 1 1 0 0 1
+netname=RS232_RXD
+}
+N 85200 40500 86900 40500 4
+{
+T 85500 40500 5 10 1 1 0 0 1
+netname=RS232_TXD
+}
+C 83600 32300 1 90 0 generic-power.sym
+{
+T 83350 32500 5 10 1 1 90 3 1
+net=AGND:1
+}
+N 83600 32500 83800 32500 4
+N 85200 41300 86500 41300 4
+{
+T 85600 41300 5 10 1 1 0 0 1
+netname=I2C_A1
+}
+N 85200 44900 85500 44900 4
+N 83800 44900 83500 44900 4
+C 85400 32700 1 270 0 generic-power.sym
+{
+T 85650 32500 5 10 1 1 270 3 1
+net=AGND:1
+}
+N 85400 32500 85200 32500 4
+N 85200 38100 86400 38100 4
+{
+T 85300 38100 5 10 1 1 0 0 1
+netname=SEN_RX
+}
+N 83800 37700 83600 37700 4
+N 85200 37700 85400 37700 4
+C 83600 36700 1 90 0 generic-power.sym
+{
+T 83350 36900 5 10 1 1 90 3 1
+net=AGND:1
+}
+N 83600 36900 83800 36900 4
+C 85400 37100 1 270 0 generic-power.sym
+{
+T 85650 36900 5 10 1 1 270 3 1
+net=AGND:1
+}
+N 85400 36900 85200 36900 4
+N 85200 33300 86800 33300 4
+{
+T 85200 33300 5 10 1 1 0 0 1
+netname=AUX_ADC_A1
+}
+N 85200 32900 86800 32900 4
+{
+T 85200 32900 5 10 1 1 0 0 1
+netname=AUX_ADC_B1
+}
+C 83600 33500 1 90 0 generic-power.sym
+{
+T 83350 33700 5 10 1 1 90 3 1
+net=AGND:1
+}
+N 83600 33700 83800 33700 4
+C 83600 34300 1 90 0 generic-power.sym
+{
+T 83350 34500 5 10 1 1 90 3 1
+net=AGND:1
+}
+N 83600 34500 83800 34500 4
+C 83600 35500 1 90 0 generic-power.sym
+{
+T 83350 35700 5 10 1 1 90 3 1
+net=AGND:1
+}
+N 83600 35700 83800 35700 4
+N 82200 32900 83800 32900 4
+{
+T 82200 32900 5 10 1 1 0 0 1
+netname=VINP_A
+}
+N 82200 33300 83800 33300 4
+{
+T 82200 33300 5 10 1 1 0 0 1
+netname=VINN_A
+}
+N 82200 35300 83800 35300 4
+{
+T 82200 35300 5 10 1 1 0 0 1
+netname=VINP_B
+}
+N 82200 34900 83800 34900 4
+{
+T 82200 34900 5 10 1 1 0 0 1
+netname=VINN_B
+}
+N 83800 34100 82200 34100 4
+{
+T 82300 34100 5 10 1 1 0 0 1
+netname=VREF
+}
+C 85400 35900 1 270 0 generic-power.sym
+{
+T 85650 35700 5 10 1 1 270 3 1
+net=AGND:1
+}
+N 85400 35700 85200 35700 4
+C 86000 36300 1 270 0 generic-power.sym
+{
+T 86250 36100 5 10 1 1 270 3 1
+net=AVDD:1
+}
+N 85200 36500 85700 36500 4
+N 85200 36100 86000 36100 4
+C 85700 36700 1 270 0 generic-power.sym
+{
+T 85950 36500 5 10 1 1 270 3 1
+net=AVDD:1
+}
+C 85900 44700 1 270 0 generic-power.sym
+{
+T 86150 44500 5 10 1 1 270 3 1
+net=6V:1
+}
+C 83000 36300 1 90 1 generic-power.sym
+{
+T 82750 36100 5 10 1 1 90 3 1
+net=AVDD:1
+}
+N 83800 36100 83000 36100 4
+N 83800 36500 83300 36500 4
+C 83300 36700 1 90 1 generic-power.sym
+{
+T 83050 36500 5 10 1 1 90 3 1
+net=AVDD:1
+}
+N 85200 44500 85900 44500 4
+N 85200 44100 85700 44100 4
+C 85700 43500 1 270 0 generic-power.sym
+{
+T 85950 43300 5 10 1 1 270 3 1
+net=DVDD:1
+}
+N 85200 43300 85700 43300 4
+N 85200 43700 85500 43700 4
+N 85700 44100 85700 44500 4
+N 85500 43700 85500 43300 4
+N 81800 44100 83800 44100 4
+{
+T 82100 44100 5 10 1 1 0 0 1
+netname=io_rx_15
+}
+N 81800 43700 83800 43700 4
+{
+T 82100 43700 5 10 1 1 0 0 1
+netname=io_rx_14
+}
+N 81800 42500 83800 42500 4
+{
+T 82100 42500 5 10 1 1 0 0 1
+netname=io_rx_11
+}
+N 81800 43300 83800 43300 4
+{
+T 82100 43300 5 10 1 1 0 0 1
+netname=io_rx_13
+}
+N 81800 42900 83800 42900 4
+{
+T 82100 42900 5 10 1 1 0 0 1
+netname=io_rx_12
+}
+N 81800 41300 83800 41300 4
+{
+T 82100 41300 5 10 1 1 0 0 1
+netname=io_rx_08
+}
+N 81800 42100 83800 42100 4
+{
+T 82100 42100 5 10 1 1 0 0 1
+netname=io_rx_10
+}
+N 81800 41700 83800 41700 4
+{
+T 82100 41700 5 10 1 1 0 0 1
+netname=io_rx_09
+}
+N 81800 40100 83800 40100 4
+{
+T 82100 40100 5 10 1 1 0 0 1
+netname=io_rx_05
+}
+N 81800 40900 83800 40900 4
+{
+T 82100 40900 5 10 1 1 0 0 1
+netname=io_rx_07
+}
+N 81800 40500 83800 40500 4
+{
+T 82100 40500 5 10 1 1 0 0 1
+netname=io_rx_06
+}
+N 81800 38900 83800 38900 4
+{
+T 82100 38900 5 10 1 1 0 0 1
+netname=io_rx_02
+}
+N 81800 39700 83800 39700 4
+{
+T 82100 39700 5 10 1 1 0 0 1
+netname=io_rx_04
+}
+N 81800 39300 83800 39300 4
+{
+T 82100 39300 5 10 1 1 0 0 1
+netname=io_rx_03
+}
+N 81800 38100 83800 38100 4
+{
+T 82100 38100 5 10 1 1 0 0 1
+netname=io_rx_00
+}
+N 81800 38500 83800 38500 4
+{
+T 82100 38500 5 10 1 1 0 0 1
+netname=io_rx_01
+}
+C 53600 29400 0 0 0 title-bordered-D.sym
+T 82500 30300 5 10 1 1 0 0 1
+date=$Date: 2005/12/12 23:48:25 $
+T 84400 30000 5 10 1 1 0 0 1
+rev=$Revision: 1.10 $
+T 84500 29700 5 10 1 1 0 0 1
+auth=$Author: matt $
+T 80300 30000 5 10 1 1 0 0 1
+fname=$Source: /opt/usrp-hw-cvs/usrp-hw/dbsrx/dbsrx.sch,v $
+T 83700 30700 8 14 1 1 0 4 1
+title=DBS Tuner Daughterboard REV 2
+T 81300 29700 9 10 1 0 0 0 1
+1
+T 82100 29700 9 10 1 0 0 0 1
+1
+N 85200 42100 86300 42100 4
+{
+T 85500 42100 5 10 1 1 0 0 1
+netname=SCL
+}
+N 85200 41700 86300 41700 4
+{
+T 85500 41700 5 10 1 1 0 0 1
+netname=SDA
+}
+N 85200 39300 86600 39300 4
+{
+T 85600 39300 5 10 1 1 0 0 1
+netname=SCLK
+}
+N 85200 38900 86600 38900 4
+{
+T 85600 38900 5 10 1 1 0 0 1
+netname=SDO
+}
+N 85200 38500 86600 38500 4
+{
+T 85600 38500 5 10 1 1 0 0 1
+netname=SDI
+}
+N 85200 34900 86900 34900 4
+{
+T 85400 34900 5 10 1 1 0 0 1
+netname=AUX_DAC_A
+}
+N 85200 34500 86900 34500 4
+{
+T 85400 34500 5 10 1 1 0 0 1
+netname=AUX_DAC_B
+}
+N 85200 34100 86900 34100 4
+{
+T 85400 34100 5 10 1 1 0 0 1
+netname=AUX_DAC_C
+}
+N 85200 33700 86900 33700 4
+{
+T 85300 33700 5 10 1 1 0 0 1
+netname=AUX_ADC_REF
+}
+N 85200 35300 86900 35300 4
+{
+T 85400 35300 5 10 1 1 0 0 1
+netname=AUX_DAC_D
+}
+C 76600 30600 1 0 0 24Cxx-1.sym
+{
+T 77100 31800 5 10 1 1 0 0 1
+refdes=U1
+T 76600 30600 5 10 0 1 0 0 1
+footprint=SO8
+T 76900 30400 5 10 1 1 0 0 1
+device=24LC024/SN
+T 76900 30000 5 10 1 1 0 0 1
+net=DGND:4
+T 76900 30200 5 10 1 1 0 0 1
+net=DVDD:8
+}
+N 77900 30900 79300 30900 4
+{
+T 78800 30900 5 10 1 1 0 0 1
+netname=SCL
+}
+N 77900 30700 79300 30700 4
+{
+T 78800 30700 5 10 1 1 0 0 1
+netname=SDA
+}
+N 77900 31100 78100 31100 4
+N 85200 40900 86500 40900 4
+{
+T 85600 40900 5 10 1 1 0 0 1
+netname=I2C_A0
+}
+N 75600 31100 76600 31100 4
+{
+T 75700 31100 5 10 1 1 0 0 1
+netname=I2C_A1
+}
+C 75600 30700 1 90 0 generic-power.sym
+{
+T 75350 30900 5 10 1 1 90 3 1
+net=DVDD:1
+}
+N 75600 30900 76600 30900 4
+N 74300 41400 73500 41400 4
+{
+T 74300 41400 5 10 1 1 0 6 1
+netname=VINP_A
+}
+N 74300 42400 73500 42400 4
+{
+T 74300 42400 5 10 1 1 0 6 1
+netname=VINN_A
+}
+C 66400 33500 1 90 1 generic-power.sym
+{
+T 66150 33300 5 10 1 1 90 3 1
+net=AVDD:1
+}
+C 69400 33500 1 270 0 generic-power.sym
+{
+T 69650 33300 5 10 1 1 270 3 1
+net=AGND:1
+}
+C 66700 33200 1 0 0 resistor-1.sym
+{
+T 67300 33600 5 10 1 1 180 0 1
+refdes=R6
+T 67300 33100 5 10 1 1 180 0 1
+value=1K
+T 66700 33200 5 10 0 1 0 0 1
+footprint=0603
+}
+C 68000 32400 1 0 0 capacitor-1.sym
+{
+T 68600 32700 5 10 1 1 0 0 1
+refdes=C24
+T 68600 32300 5 10 1 1 0 0 1
+value=.1uF
+T 68000 32400 5 10 0 1 90 0 1
+footprint=0603
+}
+C 68000 33200 1 0 0 resistor-1.sym
+{
+T 68600 33600 5 10 1 1 180 0 1
+refdes=R7
+T 68600 33100 5 10 1 1 180 0 1
+value=1K
+T 68000 33200 5 10 0 1 0 0 1
+footprint=0603
+}
+N 66400 33300 66700 33300 4
+N 67600 33300 68000 33300 4
+N 68900 33300 69400 33300 4
+N 69100 32600 68900 32600 4
+N 67800 32600 68000 32600 4
+N 67800 33300 67800 34100 4
+C 72600 42300 1 0 0 resistor-1.sym
+{
+T 73400 42700 5 10 1 1 180 0 1
+refdes=R10
+T 73300 42200 5 10 1 1 180 0 1
+value=50
+T 72600 42300 5 10 0 1 0 0 1
+footprint=0603
+}
+C 72600 41300 1 0 0 resistor-1.sym
+{
+T 73400 41700 5 10 1 1 180 0 1
+refdes=R71
+T 73300 41200 5 10 1 1 180 0 1
+value=50
+T 72600 41300 5 10 0 1 0 0 1
+footprint=0603
+}
+C 74300 42200 1 0 0 capacitor-1.sym
+{
+T 74900 42500 5 10 1 1 0 0 1
+refdes=C64
+T 74900 42100 5 10 1 1 0 0 1
+value=100pF
+T 74300 42200 5 10 0 1 90 0 1
+footprint=0603
+}
+C 74300 41200 1 0 0 capacitor-1.sym
+{
+T 74900 41500 5 10 1 1 0 0 1
+refdes=C65
+T 74900 41100 5 10 1 1 0 0 1
+value=100pF
+T 74300 41200 5 10 0 1 90 0 1
+footprint=0603
+}
+N 75200 42400 75400 42400 4
+C 75500 41900 1 270 1 generic-power.sym
+{
+T 75750 42100 5 10 1 1 270 3 1
+net=AGND:1
+}
+N 72200 42400 72600 42400 4
+N 72200 41400 72600 41400 4
+T 81100 45500 9 20 1 0 0 0 1
+REVERSE PMC on BOTTOM!!!!
+N 86600 39700 85200 39700 4
+{
+T 86200 39700 5 10 1 1 0 6 1
+netname=RESET
+}
+C 78800 36500 1 0 0 header16-1.sym
+{
+T 79300 39800 5 10 1 1 0 0 1
+refdes=J24
+T 78800 36500 5 10 0 1 0 0 1
+footprint=CONNECTOR 8 2
+}
+C 78800 32500 1 0 0 header16-1.sym
+{
+T 79300 35800 5 10 1 1 0 0 1
+refdes=J25
+T 78800 32500 5 10 0 1 0 0 1
+footprint=CONNECTOR 8 2
+}
+N 80200 38300 80500 38300 4
+N 80200 39500 80400 39500 4
+N 80400 39500 80400 38300 4
+N 80400 38300 80400 36700 4
+N 80400 36700 80200 36700 4
+N 80200 39100 80400 39100 4
+N 80200 38700 80400 38700 4
+N 80200 37900 80400 37900 4
+N 80200 37500 80400 37500 4
+N 80200 37100 80400 37100 4
+N 80200 34300 80500 34300 4
+N 80200 35500 80400 35500 4
+N 80400 35500 80400 34300 4
+N 80400 34300 80400 32700 4
+N 80400 32700 80200 32700 4
+N 80200 35100 80400 35100 4
+N 80200 34700 80400 34700 4
+N 80200 33900 80400 33900 4
+N 80200 33500 80400 33500 4
+N 80200 33100 80400 33100 4
+N 77100 35500 78800 35500 4
+{
+T 77600 35500 5 10 1 1 0 0 1
+netname=io_rx_15
+}
+N 77100 33900 78800 33900 4
+{
+T 77600 33900 5 10 1 1 0 0 1
+netname=io_rx_11
+}
+N 77100 34700 78800 34700 4
+{
+T 77600 34700 5 10 1 1 0 0 1
+netname=io_rx_13
+}
+N 77100 33100 78800 33100 4
+{
+T 77600 33100 5 10 1 1 0 0 1
+netname=io_rx_09
+}
+N 77200 38700 78800 38700 4
+{
+T 77600 38700 5 10 1 1 0 0 1
+netname=io_rx_05
+}
+N 77200 39500 78800 39500 4
+{
+T 77600 39500 5 10 1 1 0 0 1
+netname=io_rx_07
+}
+N 77200 37900 78800 37900 4
+{
+T 77600 37900 5 10 1 1 0 0 1
+netname=io_rx_03
+}
+N 77100 35100 78800 35100 4
+{
+T 77600 35100 5 10 1 1 0 0 1
+netname=io_rx_14
+}
+N 77100 34300 78800 34300 4
+{
+T 77600 34300 5 10 1 1 0 0 1
+netname=io_rx_12
+}
+N 77100 32700 78800 32700 4
+{
+T 77600 32700 5 10 1 1 0 0 1
+netname=io_rx_08
+}
+N 77100 33500 78800 33500 4
+{
+T 77600 33500 5 10 1 1 0 0 1
+netname=io_rx_10
+}
+N 77200 39100 78800 39100 4
+{
+T 77600 39100 5 10 1 1 0 0 1
+netname=io_rx_06
+}
+N 77200 37500 78800 37500 4
+{
+T 77600 37500 5 10 1 1 0 0 1
+netname=io_rx_02
+}
+N 77200 38300 78800 38300 4
+{
+T 77600 38300 5 10 1 1 0 0 1
+netname=io_rx_04
+}
+N 77200 37100 78800 37100 4
+{
+T 77600 37100 5 10 1 1 0 0 1
+netname=io_rx_01
+}
+C 70100 40500 1 0 0 ad813x.sym
+{
+T 71400 43000 5 10 1 1 0 0 1
+refdes=U5
+}
+C 70700 43300 1 0 0 generic-power.sym
+{
+T 70900 43550 5 10 1 1 180 5 1
+net=5V_RF:1
+}
+C 71100 40500 1 180 0 generic-power.sym
+{
+T 70900 40250 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 70900 40500 70900 40600 4
+N 70900 43300 70900 43200 4
+C 71600 44100 1 180 0 resistor-1.sym
+{
+T 71100 43700 5 10 1 1 0 0 1
+value=250, 0.1%
+T 71600 44100 5 10 0 1 180 0 1
+footprint=0603
+T 71100 44200 5 10 1 1 0 0 1
+refdes=R65
+}
+C 71600 40200 1 180 0 resistor-1.sym
+{
+T 71100 39800 5 10 1 1 0 0 1
+value=250, 0.1%
+T 71600 40200 5 10 0 1 180 0 1
+footprint=0603
+T 71100 40300 5 10 1 1 0 0 1
+refdes=R66
+}
+C 69900 41500 1 180 0 resistor-1.sym
+{
+T 69500 41100 5 10 1 1 0 0 1
+value=250, 0.1%
+T 69900 41500 5 10 0 1 180 0 1
+footprint=0603
+T 69200 41100 5 10 1 1 0 0 1
+refdes=R67
+}
+C 69900 42500 1 180 0 resistor-1.sym
+{
+T 69600 42600 5 10 1 1 0 0 1
+value=250, 0.1%
+T 69900 42500 5 10 0 1 180 0 1
+footprint=0603
+T 69200 42600 5 10 1 1 0 0 1
+refdes=R68
+}
+N 67800 34100 68900 34100 4
+{
+T 68000 34100 5 10 1 1 0 0 1
+netname=local_vref
+}
+N 68900 41900 70200 41900 4
+{
+T 69200 41900 5 10 1 1 0 0 1
+netname=local_vref
+}
+N 69900 41400 70200 41400 4
+N 70100 40100 70700 40100 4
+N 71600 40100 72400 40100 4
+N 69900 42400 70200 42400 4
+N 70100 44000 70700 44000 4
+N 71600 44000 72400 44000 4
+C 70700 44800 1 180 1 capacitor-1.sym
+{
+T 70600 44700 5 10 1 1 0 0 1
+refdes=C66
+T 71300 44700 5 10 1 1 0 0 1
+value=22pF
+T 70700 44800 5 10 0 1 270 2 1
+footprint=0603
+}
+C 70700 39700 1 180 1 capacitor-1.sym
+{
+T 70600 39600 5 10 1 1 0 0 1
+refdes=C67
+T 71300 39600 5 10 1 1 0 0 1
+value=22pF
+T 70700 39700 5 10 0 1 270 2 1
+footprint=0603
+}
+N 70100 39500 70100 41400 4
+N 70100 39500 70700 39500 4
+N 71600 39500 72400 39500 4
+N 72400 39500 72400 41400 4
+N 70100 42400 70100 44600 4
+N 70100 44600 70700 44600 4
+N 71600 44600 72400 44600 4
+N 72400 42400 72400 44600 4
+N 75400 42400 75400 41400 4
+N 75400 41400 75200 41400 4
+N 75400 42100 75500 42100 4
+N 73000 32900 74100 32900 4
+{
+T 73300 32900 5 10 1 1 0 0 1
+netname=SDA
+}
+N 73000 32500 74100 32500 4
+{
+T 73300 32500 5 10 1 1 0 0 1
+netname=SCL
+}
+C 74000 32000 1 0 0 max211x-DIG.sym
+{
+T 75300 34800 5 10 1 1 0 6 1
+refdes=U3
+}
+C 57500 32100 1 0 0 max211x-PLL.sym
+{
+T 58800 34500 5 10 1 1 0 6 1
+refdes=U3
+}
+C 60500 36100 1 0 0 max211x-PWR.sym
+{
+T 61700 42900 5 10 1 1 0 6 1
+refdes=U3
+}
+C 65100 44800 1 0 0 max211x-SIG.sym
+{
+T 66600 47300 5 10 1 1 0 6 1
+refdes=U3
+}
+C 62900 41600 1 0 0 capacitor-1.sym
+{
+T 63500 41900 5 10 1 1 0 0 1
+refdes=C68
+T 63500 41500 5 10 1 1 0 0 1
+value=.1uF
+T 62900 41600 5 10 0 1 90 0 1
+footprint=0603
+}
+N 62600 41800 62900 41800 4
+N 62600 42200 63900 42200 4
+N 63900 42200 63900 41800 4
+N 63900 41800 63800 41800 4
+C 62900 40800 1 0 0 capacitor-1.sym
+{
+T 63500 41100 5 10 1 1 0 0 1
+refdes=C69
+T 63500 40700 5 10 1 1 0 0 1
+value=.1uF
+T 62900 40800 5 10 0 1 90 0 1
+footprint=0603
+}
+N 62600 41000 62900 41000 4
+N 62600 41400 63900 41400 4
+N 63900 41400 63900 41000 4
+N 63900 41000 63800 41000 4
+C 63600 40400 1 0 0 capacitor-1.sym
+{
+T 64200 40700 5 10 1 1 0 0 1
+refdes=C70
+T 64200 40300 5 10 1 1 0 0 1
+value=.22uF
+T 63600 40400 5 10 0 1 90 0 1
+footprint=0603
+}
+C 63000 40000 1 0 0 capacitor-1.sym
+{
+T 63600 40300 5 10 1 1 0 0 1
+refdes=C71
+T 63600 39900 5 10 1 1 0 0 1
+value=.22uF
+T 63000 40000 5 10 0 1 90 0 1
+footprint=0603
+}
+N 62600 40200 63000 40200 4
+N 62600 40600 63600 40600 4
+C 65000 39600 1 180 0 generic-power.sym
+{
+T 64800 39350 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 63900 40200 64800 40200 4
+N 64800 39600 64800 40600 4
+N 64800 40600 64500 40600 4
+C 60100 36300 1 180 0 generic-power.sym
+{
+T 59900 36050 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 59900 36300 59900 39400 4
+N 59900 39400 60600 39400 4
+N 59900 39000 60600 39000 4
+N 59900 38200 60600 38200 4
+N 59900 38600 60600 38600 4
+N 59900 37400 60600 37400 4
+N 59900 37800 60600 37800 4
+N 59900 36600 60600 36600 4
+C 62500 46400 1 0 0 resistor-1.sym
+{
+T 62800 46800 5 10 1 1 180 0 1
+refdes=R9
+T 63400 46800 5 10 1 1 180 0 1
+value=43.2
+T 62500 46400 5 10 0 1 0 0 1
+footprint=0603
+}
+C 54300 45700 1 180 1 generic-power.sym
+{
+T 54500 45450 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 54500 46000 54500 45700 4
+N 54900 46500 56500 46500 4
+C 61300 45100 1 180 1 generic-power.sym
+{
+T 61500 44850 5 10 1 1 180 3 1
+net=AGND:1
+}
+C 56500 46700 1 180 1 capacitor-1.sym
+{
+T 56800 46700 5 10 1 1 0 6 1
+refdes=C99
+T 56600 46200 5 10 1 1 180 6 1
+value=47pF
+T 56500 46700 5 10 0 1 270 2 1
+footprint=0603
+}
+N 57400 46500 57700 46500 4
+C 60200 46700 1 180 1 capacitor-1.sym
+{
+T 60800 46600 5 10 1 1 0 0 1
+refdes=C96
+T 60800 46400 5 10 1 1 180 6 1
+value=47pF
+T 60200 46700 5 10 0 1 270 2 1
+footprint=0603
+}
+N 59400 46500 60200 46500 4
+N 59900 46500 59900 46800 4
+N 59900 47700 59900 48100 4
+C 60600 48700 1 180 1 capacitor-1.sym
+{
+T 61200 48600 5 10 1 1 0 0 1
+refdes=C98
+T 61200 48400 5 10 1 1 180 6 1
+value=10nF
+T 60600 48700 5 10 0 1 270 2 1
+footprint=0603
+}
+C 60600 48100 1 180 1 capacitor-1.sym
+{
+T 61200 48000 5 10 1 1 0 0 1
+refdes=C97
+T 61200 47800 5 10 1 1 180 6 1
+value=100pF
+T 60600 48100 5 10 0 1 270 2 1
+footprint=0603
+}
+N 59900 47900 60600 47900 4
+N 60400 47900 60400 48500 4
+N 60400 48500 60600 48500 4
+C 62300 48000 1 270 1 generic-power.sym
+{
+T 62550 48200 5 10 1 1 270 3 1
+net=AGND:1
+}
+N 62300 48200 62000 48200 4
+N 62000 48500 61500 48500 4
+N 61500 47900 62000 47900 4
+N 62000 47900 62000 48500 4
+C 61600 45400 1 90 0 resistor-1.sym
+{
+T 61700 45800 5 10 1 1 0 0 1
+refdes=R40
+T 61700 45600 5 10 1 1 0 0 1
+value=86.6
+T 61600 45400 5 10 0 1 90 0 1
+footprint=0603
+}
+C 62900 46000 1 0 0 resistor-1.sym
+{
+T 63700 46400 5 10 1 1 180 0 1
+refdes=R11
+T 63600 45900 5 10 1 1 180 0 1
+value=75
+T 62900 46000 5 10 0 1 0 0 1
+footprint=0603
+}
+C 63600 46700 1 180 1 capacitor-1.sym
+{
+T 63900 46600 5 10 1 1 0 6 1
+refdes=C72
+T 64200 46700 5 10 1 1 180 6 1
+value=47pF
+T 63600 46700 5 10 0 1 270 2 1
+footprint=0603
+}
+C 64200 46300 1 180 1 capacitor-1.sym
+{
+T 64500 46200 5 10 1 1 0 6 1
+refdes=C73
+T 64800 46300 5 10 1 1 180 6 1
+value=47pF
+T 64200 46300 5 10 0 1 270 2 1
+footprint=0603
+}
+N 65100 46100 65200 46100 4
+N 64500 46500 65200 46500 4
+N 63800 46100 64200 46100 4
+N 63400 46500 63600 46500 4
+N 61500 45100 61500 45400 4
+N 61500 46500 61500 46300 4
+C 62100 45500 1 180 1 generic-power.sym
+{
+T 62300 45250 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 62300 45500 62300 46100 4
+N 62300 46100 62900 46100 4
+N 61100 46500 62500 46500 4
+C 58600 42000 1 0 0 capacitor-1.sym
+{
+T 59200 42300 5 10 1 1 0 0 1
+refdes=C74
+T 59200 42000 5 10 1 1 0 0 1
+value=1000pF
+T 58600 42000 5 10 0 1 90 0 1
+footprint=0603
+}
+C 58000 41600 1 0 0 capacitor-1.sym
+{
+T 58600 41900 5 10 1 1 0 0 1
+refdes=C75
+T 58600 41600 5 10 1 1 0 0 1
+value=1000pF
+T 58000 41600 5 10 0 1 90 0 1
+footprint=0603
+}
+C 58600 40800 1 0 0 capacitor-1.sym
+{
+T 59200 41100 5 10 1 1 0 0 1
+refdes=C76
+T 59200 40800 5 10 1 1 0 0 1
+value=1000pF
+T 58600 40800 5 10 0 1 90 0 1
+footprint=0603
+}
+C 58000 40400 1 0 0 capacitor-1.sym
+{
+T 58600 40700 5 10 1 1 0 0 1
+refdes=C77
+T 58600 40400 5 10 1 1 0 0 1
+value=1000pF
+T 58000 40400 5 10 0 1 90 0 1
+footprint=0603
+}
+C 58900 40000 1 0 0 capacitor-1.sym
+{
+T 59500 40300 5 10 1 1 0 0 1
+refdes=C78
+T 59500 40000 5 10 1 1 0 0 1
+value=1000pF
+T 58900 40000 5 10 0 1 90 0 1
+footprint=0603
+}
+C 58300 39600 1 0 0 capacitor-1.sym
+{
+T 58900 39900 5 10 1 1 0 0 1
+refdes=C79
+T 58900 39600 5 10 1 1 0 0 1
+value=1000pF
+T 58300 39600 5 10 0 1 90 0 1
+footprint=0603
+}
+N 59500 42200 60600 42200 4
+{
+T 59800 42200 5 10 1 1 0 0 1
+netname=5V_RF
+}
+N 59500 41000 60600 41000 4
+{
+T 59800 41000 5 10 1 1 0 0 1
+netname=5V_RF
+}
+N 58900 41800 60600 41800 4
+{
+T 59800 41800 5 10 1 1 0 0 1
+netname=5V_RF
+}
+N 59200 39800 60600 39800 4
+{
+T 59800 39800 5 10 1 1 0 0 1
+netname=5V_RF
+}
+N 58900 40600 60600 40600 4
+{
+T 59800 40600 5 10 1 1 0 0 1
+netname=5V_RF
+}
+N 59800 40200 60600 40200 4
+{
+T 59900 40200 5 10 1 1 0 0 1
+netname=5V_RF
+}
+N 58600 42200 57900 42200 4
+N 57900 39800 58300 39800 4
+N 58900 40200 57900 40200 4
+N 57900 40600 58000 40600 4
+N 57900 41000 58600 41000 4
+N 57900 41800 58000 41800 4
+N 60600 41400 59300 41400 4
+{
+T 59600 41400 5 10 1 1 0 0 1
+netname=VccVCO
+}
+C 58100 39400 1 180 0 generic-power.sym
+{
+T 57900 39150 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 57900 39400 57900 42200 4
+N 56000 39800 57300 39800 4
+{
+T 57300 39800 5 10 1 1 0 6 1
+netname=VccVCO
+}
+C 56500 41900 1 0 1 generic-power.sym
+{
+T 56300 42150 5 10 1 1 180 5 1
+net=5V_RF:1
+}
+C 56000 40100 1 0 1 capacitor-1.sym
+{
+T 55400 40400 5 10 1 1 0 6 1
+refdes=C80
+T 55400 40100 5 10 1 1 0 6 1
+value=1000pF
+T 56000 40100 5 10 0 1 90 2 1
+footprint=0603
+}
+C 56000 41500 1 0 1 capacitor-1.sym
+{
+T 55400 41800 5 10 1 1 0 6 1
+refdes=C81
+T 55400 41500 5 10 1 1 0 6 1
+value=1000pF
+T 56000 41500 5 10 0 1 90 2 1
+footprint=0603
+}
+C 56200 40500 1 270 1 resistor-1.sym
+{
+T 56100 41000 5 10 1 1 0 6 1
+refdes=R12
+T 56100 40700 5 10 1 1 0 6 1
+value=4.7
+T 56200 40500 5 10 0 1 90 2 1
+footprint=0603
+}
+C 56000 39600 1 0 1 capacitor-2.sym
+{
+T 55400 39600 5 10 1 1 0 6 1
+refdes=C82
+T 56200 39600 5 10 1 1 0 6 1
+value=100uF
+T 56000 39600 5 10 0 1 90 2 1
+footprint=EIA6032
+}
+N 56300 41900 56300 41400 4
+N 56000 41700 56300 41700 4
+N 55100 41700 54500 41700 4
+N 54500 39800 55100 39800 4
+N 55100 40300 54500 40300 4
+N 56300 40500 56300 39800 4
+N 56000 40300 56300 40300 4
+C 54700 39500 1 180 0 generic-power.sym
+{
+T 54500 39250 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 54500 39500 54500 41700 4
+N 71100 32800 72100 32800 4
+{
+T 71200 32800 5 10 1 1 0 0 1
+netname=I2C_A1
+}
+T 71900 30900 9 10 1 0 0 0 4
+We invert A1 which tells us which
+side we're on, A or B
+Leave other addresses open (high)
+A2,A0 will match EEPROM
+C 57400 31400 1 180 0 generic-power.sym
+{
+T 57200 31150 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 57200 31400 57200 31600 4
+C 57000 33600 1 270 0 capacitor-1.sym
+{
+T 57200 33400 5 10 1 1 180 0 1
+refdes=C61
+T 57200 32900 5 10 1 1 0 6 1
+value=.1uF
+T 57000 33600 5 10 0 1 0 0 1
+footprint=0603
+}
+N 57200 32500 57200 32700 4
+N 57200 33800 57200 33600 4
+C 57000 34000 1 180 0 capacitor-1.sym
+{
+T 56100 33900 5 10 1 1 0 0 1
+refdes=C63
+T 56700 33900 5 10 1 1 0 0 1
+value=.1uF
+T 57000 34000 5 10 0 1 270 0 1
+footprint=0603
+}
+N 53800 33800 54800 33800 4
+{
+T 53900 33800 5 10 1 1 0 0 1
+netname=io_rx_00
+}
+C 60100 32300 1 90 0 capacitor-1.sym
+{
+T 59500 32500 5 10 1 1 0 0 1
+refdes=C83
+T 59400 32300 5 10 1 1 0 0 1
+value=.01uF
+T 60100 32300 5 10 0 1 180 0 1
+footprint=0603
+}
+C 60800 33300 1 0 0 resistor-1.sym
+{
+T 61400 33700 5 10 1 1 180 0 1
+refdes=R13
+T 61400 33200 5 10 1 1 180 0 1
+value=1K
+T 60800 33300 5 10 0 1 0 0 1
+footprint=0603
+}
+C 61700 33200 1 270 0 capacitor-1.sym
+{
+T 62500 33000 5 10 1 1 180 0 1
+refdes=C59
+T 62000 32500 5 10 1 1 0 0 1
+value=3300pF
+T 61700 33200 5 10 0 1 0 0 1
+footprint=0603
+}
+C 60100 31200 1 270 1 capacitor-1.sym
+{
+T 60700 31400 5 10 1 1 0 6 1
+refdes=C84
+T 60800 31200 5 10 1 1 0 6 1
+value=.1uF
+T 60100 31200 5 10 0 1 180 6 1
+footprint=0603
+}
+C 60200 32300 1 270 1 resistor-1.sym
+{
+T 60700 32800 5 10 1 1 0 6 1
+refdes=R14
+T 61000 32500 5 10 1 1 0 6 1
+value=2.21K
+T 60200 32300 5 10 0 1 90 2 1
+footprint=0603
+}
+C 60300 30900 1 180 0 generic-power.sym
+{
+T 60100 30650 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 60300 31200 60300 31100 4
+N 59900 31100 59900 32300 4
+N 60300 32100 60300 32300 4
+N 60100 30900 60100 31100 4
+N 59600 33400 60800 33400 4
+N 60300 33200 60300 33400 4
+N 59900 33200 59900 33400 4
+N 61700 33400 61900 33400 4
+N 59600 33800 61900 33800 4
+N 61900 33200 61900 33800 4
+N 59900 31100 61900 31100 4
+N 61900 31100 61900 32300 4
+N 74300 47600 73500 47600 4
+{
+T 74300 47600 5 10 1 1 0 6 1
+netname=VINP_B
+}
+N 74300 48600 73500 48600 4
+{
+T 74300 48600 5 10 1 1 0 6 1
+netname=VINN_B
+}
+C 72600 48500 1 0 0 resistor-1.sym
+{
+T 73400 48900 5 10 1 1 180 0 1
+refdes=R15
+T 73300 48400 5 10 1 1 180 0 1
+value=50
+T 72600 48500 5 10 0 1 0 0 1
+footprint=0603
+}
+C 72600 47500 1 0 0 resistor-1.sym
+{
+T 73400 47900 5 10 1 1 180 0 1
+refdes=R16
+T 73300 47400 5 10 1 1 180 0 1
+value=50
+T 72600 47500 5 10 0 1 0 0 1
+footprint=0603
+}
+C 74300 48400 1 0 0 capacitor-1.sym
+{
+T 74900 48700 5 10 1 1 0 0 1
+refdes=C25
+T 74900 48300 5 10 1 1 0 0 1
+value=100pF
+T 74300 48400 5 10 0 1 90 0 1
+footprint=0603
+}
+C 74300 47400 1 0 0 capacitor-1.sym
+{
+T 74900 47700 5 10 1 1 0 0 1
+refdes=C26
+T 74900 47300 5 10 1 1 0 0 1
+value=100pF
+T 74300 47400 5 10 0 1 90 0 1
+footprint=0603
+}
+N 75200 48600 75400 48600 4
+C 75500 48000 1 270 1 generic-power.sym
+{
+T 75750 48200 5 10 1 1 270 3 1
+net=AGND:1
+}
+N 72200 48600 72600 48600 4
+N 72200 47600 72600 47600 4
+C 70100 46700 1 0 0 ad813x.sym
+{
+T 71400 49200 5 10 1 1 0 0 1
+refdes=U6
+}
+C 70700 49500 1 0 0 generic-power.sym
+{
+T 70900 49750 5 10 1 1 180 5 1
+net=5V_RF:1
+}
+C 71100 46700 1 180 0 generic-power.sym
+{
+T 70900 46450 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 70900 46700 70900 46800 4
+N 70900 49500 70900 49400 4
+C 71600 50400 1 180 0 resistor-1.sym
+{
+T 71100 50000 5 10 1 1 0 0 1
+value=250, 0.1%
+T 71600 50400 5 10 0 1 180 0 1
+footprint=0603
+T 71100 50500 5 10 1 1 0 0 1
+refdes=R17
+}
+C 71600 46200 1 180 0 resistor-1.sym
+{
+T 71100 45800 5 10 1 1 0 0 1
+value=250, 0.1%
+T 71600 46200 5 10 0 1 180 0 1
+footprint=0603
+T 71100 46300 5 10 1 1 0 0 1
+refdes=R18
+}
+C 69900 47700 1 180 0 resistor-1.sym
+{
+T 69500 47300 5 10 1 1 0 0 1
+value=250, 0.1%
+T 69900 47700 5 10 0 1 180 0 1
+footprint=0603
+T 69200 47300 5 10 1 1 0 0 1
+refdes=R19
+}
+C 69900 48700 1 180 0 resistor-1.sym
+{
+T 69600 48800 5 10 1 1 0 0 1
+value=250, 0.1%
+T 69900 48700 5 10 0 1 180 0 1
+footprint=0603
+T 69200 48800 5 10 1 1 0 0 1
+refdes=R20
+}
+N 68900 48100 70200 48100 4
+{
+T 69300 48100 5 10 1 1 0 0 1
+netname=local_vref
+}
+N 69900 47600 70200 47600 4
+N 70100 46100 70700 46100 4
+N 71600 46100 72400 46100 4
+N 69900 48600 70200 48600 4
+N 70100 50300 70700 50300 4
+N 71600 50300 72400 50300 4
+C 70700 51100 1 180 1 capacitor-1.sym
+{
+T 70600 51000 5 10 1 1 0 0 1
+refdes=C85
+T 71300 51000 5 10 1 1 0 0 1
+value=22pF
+T 67300 42700 5 10 0 1 270 2 1
+footprint=0603
+}
+C 70700 45700 1 180 1 capacitor-1.sym
+{
+T 70600 45600 5 10 1 1 0 0 1
+refdes=C86
+T 71300 45600 5 10 1 1 0 0 1
+value=22pF
+T 70700 45700 5 10 0 1 270 2 1
+footprint=0603
+}
+N 70100 45500 70100 47600 4
+N 70100 45500 70700 45500 4
+N 71600 45500 72400 45500 4
+N 72400 45500 72400 47600 4
+N 70100 48600 70100 50900 4
+N 70100 50900 70700 50900 4
+N 71600 50900 72400 50900 4
+N 72400 48600 72400 50900 4
+N 75400 48600 75400 47600 4
+N 75400 47600 75200 47600 4
+N 75400 48200 75500 48200 4
+N 67200 45300 67600 45300 4
+N 68100 47600 69000 47600 4
+N 67200 45700 68100 45700 4
+N 67200 46500 67600 46500 4
+N 68100 42400 69000 42400 4
+N 67200 46100 68100 46100 4
+N 72600 33400 72600 33700 4
+N 72600 33700 74100 33700 4
+N 72600 32300 72600 32600 4
+N 62700 45400 64100 45400 4
+{
+T 62800 45400 5 10 1 1 0 0 1
+netname=AUX_DAC_A
+}
+N 63000 45100 64100 45100 4
+{
+T 63200 45100 5 10 1 1 0 0 1
+netname=io_rx_03
+}
+C 65000 45500 1 180 0 resistor-1.sym
+{
+T 64600 45600 5 10 1 1 0 0 1
+value=1K
+T 65000 45500 5 10 0 1 180 0 1
+footprint=0603
+T 64200 45600 5 10 1 1 0 0 1
+refdes=R21
+}
+C 65000 45000 1 0 1 resistor-1.sym
+{
+T 64600 44900 5 10 1 1 180 6 1
+value=NONE
+T 65000 45000 5 10 0 1 0 6 1
+footprint=0603
+T 64200 44900 5 10 1 1 180 6 1
+refdes=R22
+}
+C 64900 44000 1 270 1 capacitor-1.sym
+{
+T 65200 44200 5 10 1 1 0 0 1
+refdes=C87
+T 65200 44600 5 10 1 1 0 0 1
+value=.01uF
+T 64900 44000 5 10 0 1 0 2 1
+footprint=0603
+}
+N 65200 45700 65100 45700 4
+N 65100 45700 65100 44900 4
+N 65000 45400 65100 45400 4
+N 65000 45100 65100 45100 4
+C 64900 43800 1 180 1 generic-power.sym
+{
+T 65100 43550 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 65100 43800 65100 44000 4
+N 67600 46500 67600 48600 4
+N 67600 48600 69000 48600 4
+N 68100 46100 68100 47600 4
+N 68100 45700 68100 42400 4
+N 67600 45300 67600 41400 4
+N 67600 41400 69000 41400 4
+C 76500 46600 1 90 1 capacitor-1.sym
+{
+T 76600 46200 5 10 1 1 0 0 1
+refdes=C27
+T 76600 46000 5 10 1 1 0 0 1
+value=.1uF
+T 76500 46600 5 10 0 1 180 2 1
+footprint=0603
+}
+C 77400 46600 1 90 1 capacitor-1.sym
+{
+T 77500 46200 5 10 1 1 0 0 1
+refdes=C28
+T 77500 46000 5 10 1 1 0 0 1
+value=1000pF
+T 77400 46600 5 10 0 1 180 2 1
+footprint=0603
+}
+N 76300 46600 76300 46800 4
+N 76300 46800 77200 46800 4
+N 77200 46800 77200 46600 4
+N 76300 45700 76300 45500 4
+N 76300 45500 77200 45500 4
+N 77200 45500 77200 45700 4
+C 76500 46900 1 0 0 generic-power.sym
+{
+T 76700 47150 5 10 1 1 180 5 1
+net=5V_RF:1
+}
+N 76700 46900 76700 46800 4
+C 76900 45400 1 180 0 generic-power.sym
+{
+T 76700 45150 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 76700 45400 76700 45500 4
+C 54400 46000 1 0 0 SMA-5.sym
+{
+T 54400 46800 5 10 1 1 0 0 1
+refdes=J3
+T 54400 46000 5 10 0 1 0 0 1
+footprint=SMA_VERT
+}
+C 72100 32600 1 0 0 nmos-sot23.sym
+{
+T 72800 33200 5 10 1 1 0 0 1
+refdes=Q1
+}
+C 72800 32300 1 180 0 generic-power.sym
+{
+T 72600 32050 5 10 1 1 180 3 1
+net=AGND:1
+}
+C 78100 31300 1 270 0 generic-power.sym
+{
+T 78350 31100 5 10 1 1 270 3 1
+net=DGND:1
+}
+C 80500 34500 1 270 0 generic-power.sym
+{
+T 80750 34300 5 10 1 1 270 3 1
+net=DGND:1
+}
+C 80500 38500 1 270 0 generic-power.sym
+{
+T 80750 38300 5 10 1 1 270 3 1
+net=DGND:1
+}
+C 85500 45100 1 270 0 generic-power.sym
+{
+T 85750 44900 5 10 1 1 270 3 1
+net=DGND:1
+}
+C 83500 44700 1 90 0 generic-power.sym
+{
+T 83250 44900 5 10 1 1 90 3 1
+net=DGND:1
+}
+C 83600 37500 1 90 0 generic-power.sym
+{
+T 83350 37700 5 10 1 1 90 3 1
+net=DGND:1
+}
+C 85400 37900 1 270 0 generic-power.sym
+{
+T 85650 37700 5 10 1 1 270 3 1
+net=DGND:1
+}
+C 54000 43900 1 0 0 connector2-1.sym
+{
+T 54000 44700 5 10 1 1 0 0 1
+refdes=J100
+T 54000 43900 5 10 0 1 0 0 1
+footprint=CONNECTOR 1 2
+}
+C 55900 44800 1 90 0 inductor-1.sym
+{
+T 55700 45300 5 10 1 1 180 0 1
+refdes=L100
+T 55900 44800 5 10 0 1 90 0 1
+footprint=0603
+T 55200 45000 5 10 1 1 0 0 1
+value=27nH
+}
+C 55600 43900 1 180 1 generic-power.sym
+{
+T 55800 43650 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 55700 44400 55800 44400 4
+N 55800 44400 55800 44800 4
+N 55800 44100 55800 43900 4
+N 55800 45700 55800 46500 4
+C 56600 44300 1 270 1 capacitor-1.sym
+{
+T 56900 44900 5 10 1 1 0 0 1
+refdes=C100
+T 57400 44500 5 10 1 1 0 6 1
+value=.1uF
+T 56600 44300 5 10 0 1 0 2 1
+footprint=0603
+}
+N 55700 44100 56800 44100 4
+N 56800 44100 56800 44300 4
+N 55800 44700 56200 44700 4
+N 56200 44700 56200 45400 4
+N 56800 45400 56800 45200 4
+C 82100 49600 1 270 0 lm2940imp.sym
+{
+T 83600 49300 5 10 1 1 0 6 1
+refdes=U2
+}
+C 83000 46900 1 180 0 generic-power.sym
+{
+T 82800 46650 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 82600 47500 82600 47300 4
+N 83000 47300 83000 47500 4
+N 82800 46900 82800 47300 4
+C 79500 49900 1 0 0 generic-power.sym
+{
+T 79700 50150 5 10 1 1 0 3 1
+net=6V:1
+}
+N 79700 49200 79700 49900 4
+C 83900 49900 1 0 0 generic-power.sym
+{
+T 84100 50150 5 10 1 1 180 5 1
+net=5V_RF:1
+}
+N 84100 48900 84100 49900 4
+C 84300 48900 1 90 1 capacitor-2.sym
+{
+T 84600 48100 5 10 1 1 0 6 1
+refdes=C182
+T 84700 48600 5 10 1 1 0 6 1
+value=22uF
+T 84300 48900 5 10 0 1 180 2 1
+footprint=EIA6032
+}
+N 84100 47300 84100 48000 4
+N 83000 49500 83000 49700 4
+N 83000 49700 84100 49700 4
+N 82600 49700 82600 49500 4
+C 79500 48300 1 270 1 capacitor-1.sym
+{
+T 79300 48900 5 10 1 1 0 0 1
+refdes=C187
+T 79300 48500 5 10 1 1 0 0 1
+value=.1uF
+T 79500 48300 5 10 0 1 0 2 1
+footprint=0603
+}
+N 79700 48300 79700 47300 4
+C 57700 45800 1 0 0 mga82563.sym
+{
+T 58300 47100 5 10 1 1 0 0 1
+refdes=U4
+T 58500 46500 5 10 0 1 0 0 1
+footprint=SC70_6
+}
+C 59800 47700 1 270 0 inductor-1.sym
+{
+T 60100 47200 5 10 1 1 0 0 1
+refdes=L98
+T 59800 47700 5 10 0 1 270 0 1
+footprint=0603
+T 60100 47000 5 10 1 1 0 0 1
+value=27nH
+}
+C 58700 45200 1 180 0 generic-power.sym
+{
+T 58500 44950 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 58100 45800 58100 45500 4
+N 58100 45500 58900 45500 4
+N 58900 45500 58900 45800 4
+N 58600 45500 58600 45800 4
+N 58300 45500 58300 45800 4
+N 58500 45200 58500 45500 4
+C 68000 31800 1 0 0 capacitor-1.sym
+{
+T 68600 32100 5 10 1 1 0 0 1
+refdes=C124
+T 68600 31700 5 10 1 1 0 0 1
+value=1000pF
+T 68000 31800 5 10 0 1 90 0 1
+footprint=0603
+}
+N 67800 32000 67800 33300 4
+N 67800 32000 68000 32000 4
+N 69100 32000 69100 33300 4
+N 69100 32000 68900 32000 4
+C 79800 49600 1 0 0 inductor-1.sym
+{
+T 80000 49900 5 10 1 1 0 0 1
+refdes=L600
+T 79800 49600 5 10 0 1 0 0 1
+footprint=1206
+}
+C 79900 47300 1 180 0 generic-power.sym
+{
+T 79700 47050 5 10 1 1 180 3 1
+net=DGND:1
+}
+C 80900 49600 1 0 0 inductor-1.sym
+{
+T 81100 49900 5 10 1 1 0 0 1
+refdes=L601
+T 80900 49600 5 10 0 1 0 0 1
+footprint=1206
+}
+N 82600 49700 81800 49700 4
+N 80900 49700 80700 49700 4
+N 79800 49700 79700 49700 4
+C 80600 48300 1 270 1 capacitor-1.sym
+{
+T 80300 48900 5 10 1 1 0 0 1
+refdes=C183
+T 80400 48500 5 10 1 1 0 0 1
+value=.1uF
+T 80600 48300 5 10 0 1 0 2 1
+footprint=0603
+}
+N 80800 49700 80800 49200 4
+N 80800 47300 80800 48300 4
+N 80800 47300 84100 47300 4
+N 81900 47300 81900 48300 4
+C 81700 48300 1 270 1 capacitor-1.sym
+{
+T 81400 48900 5 10 1 1 0 0 1
+refdes=C184
+T 81500 48500 5 10 1 1 0 0 1
+value=.1uF
+T 81700 48300 5 10 0 1 0 2 1
+footprint=0603
+}
+N 81900 49700 81900 49200 4
+C 75600 31100 1 90 0 generic-power.sym
+{
+T 75350 31300 5 10 1 1 90 3 1
+net=DVDD:1
+}
+N 75600 31300 76600 31300 4
+C 60100 48100 1 0 1 generic-power.sym
+{
+T 59900 48350 5 10 1 1 0 3 1
+net=AVDD:1
+}
+N 59900 37000 60600 37000 4
+C 57100 32500 1 270 0 resistor-1.sym
+{
+T 57000 32000 5 10 1 1 0 6 1
+refdes=R93
+T 57000 31800 5 10 1 1 0 6 1
+value=50
+T 57100 32500 5 10 0 1 270 0 1
+footprint=0603
+}
+C 55700 33300 1 270 0 capacitor-1.sym
+{
+T 55900 33100 5 10 1 1 180 0 1
+refdes=C261
+T 55900 32600 5 10 1 1 0 6 1
+value=200pF
+T 55700 33300 5 10 0 1 0 0 1
+footprint=0603
+}
+C 54800 33700 1 0 0 resistor-1.sym
+{
+T 55300 33600 5 10 1 1 90 6 1
+refdes=R193
+T 55500 33600 5 10 1 1 90 6 1
+value=10
+T 54800 33700 5 10 0 1 0 0 1
+footprint=0603
+}
+N 55900 33300 55900 33800 4
+C 56100 32100 1 180 0 generic-power.sym
+{
+T 55900 31850 5 10 1 1 180 3 1
+net=DGND:1
+}
+N 55900 32100 55900 32400 4
+N 57000 33800 57600 33800 4
+N 55700 33800 56100 33800 4
+N 85200 42900 86300 42900 4
+{
+T 85500 42900 5 10 1 1 0 0 1
+netname=clock_p
+}
+N 53800 34000 54800 34000 4
+{
+T 54000 34000 5 10 1 1 0 0 1
+netname=clock_p
+}
+C 55700 34100 1 180 0 resistor-1.sym
+{
+T 55600 34400 5 10 1 1 0 6 1
+refdes=R194
+T 55600 34200 5 10 1 1 0 6 1
+value=NONE
+T 55700 34100 5 10 0 1 180 0 1
+footprint=0603
+}
+N 55700 34000 55800 34000 4
+N 55800 34000 55800 33800 4
+C 59500 43800 1 0 1 connector2-1.sym
+{
+T 59500 44600 5 10 1 1 0 6 1
+refdes=J101
+T 59500 43800 5 10 0 1 0 6 1
+footprint=CONNECTOR 1 2
+}
+N 57600 44300 57600 45400 4
+N 56200 45400 57600 45400 4
+C 57600 44200 1 90 1 generic-power.sym
+{
+T 57350 44000 5 10 1 1 270 5 1
+net=5V_RF:1
+}
+N 57800 44300 57600 44300 4
+N 57800 44000 57600 44000 4
diff --git a/usrp-hw/dbsrx/gnetlistrc b/usrp-hw/dbsrx/gnetlistrc
new file mode 100644
index 000000000..6bbd9c292
--- /dev/null
+++ b/usrp-hw/dbsrx/gnetlistrc
@@ -0,0 +1,3 @@
+(component-library "../sym")
+(component-library "../sym/generated")
+
diff --git a/usrp-hw/dbsrx/gschemrc b/usrp-hw/dbsrx/gschemrc
new file mode 100644
index 000000000..6bbd9c292
--- /dev/null
+++ b/usrp-hw/dbsrx/gschemrc
@@ -0,0 +1,3 @@
+(component-library "../sym")
+(component-library "../sym/generated")
+
diff --git a/usrp-hw/dbsrx/netlist_cmd b/usrp-hw/dbsrx/netlist_cmd
new file mode 100755
index 000000000..64f5d8af7
--- /dev/null
+++ b/usrp-hw/dbsrx/netlist_cmd
@@ -0,0 +1,3 @@
+gsch2pcb dbsrx.prj
+gnetlist -g partslist3 -o dbsrx.bom dbsrx.sch
+
diff --git a/usrp-hw/rfx/common.sch b/usrp-hw/rfx/common.sch
new file mode 100644
index 000000000..846421e94
--- /dev/null
+++ b/usrp-hw/rfx/common.sch
@@ -0,0 +1,683 @@
+v 20050820 1
+C 39500 25900 0 0 0 title-C.sym
+C 53900 40600 1 0 1 BNC-1.sym
+{
+T 53900 41400 5 10 1 1 0 6 1
+refdes=J200
+T 53900 40600 5 10 0 1 0 0 1
+footprint=SMA_VERT
+}
+C 54000 40300 1 180 0 generic-power.sym
+{
+T 53800 40050 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 53800 40600 53800 40300 4
+C 44000 40500 1 180 0 capacitor-1.sym
+{
+T 43700 40400 5 10 1 1 0 0 1
+refdes=C201
+T 44400 40100 5 10 1 1 0 6 1
+value=220pF
+T 44000 40500 5 10 0 1 270 0 1
+footprint=0603
+}
+C 42500 40900 1 180 1 capacitor-1.sym
+{
+T 42900 40800 5 10 1 1 180 2 1
+refdes=C202
+T 42900 40500 5 10 1 1 180 2 1
+value=220pF
+T 42500 40900 5 10 0 1 270 2 1
+footprint=0603
+}
+C 43800 38400 1 180 1 generic-power.sym
+{
+T 44000 38150 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 44000 40300 44500 40300 4
+N 44500 40700 43400 40700 4
+N 43100 40300 42000 40300 4
+{
+T 42100 40300 5 10 1 1 0 0 1
+netname=RF_TX
+}
+N 41200 30600 44800 30600 4
+{
+T 41500 30600 5 10 1 1 0 0 1
+netname=io_tx_06
+}
+T 40300 26300 9 15 1 0 0 0 6
+Band
+400 - 500 MHz
+800 - 975 MHz
+1.2 - 1.3 GHz
+2.3 - 2.4 GHz
+2.4 - 2.7 GHz
+T 47100 26300 9 15 1 0 0 0 6
+Upconverter VCO
+ADF4360-7 (Div by 2)
+ADF4360-3 (Div by 2)
+ADF4360-0 (Div by 2)
+ADF4360-1
+ADF4360-0
+T 42900 26300 9 15 1 0 0 0 6
+Upconverter
+AD8345
+AD8349
+AD8349
+AD8349
+AD8349
+T 44900 26300 9 15 1 0 0 0 6
+Downconverter
+AD8348
+AD8347
+AD8347
+AD8347
+AD8347
+T 50300 26300 9 15 1 0 0 0 6
+Downconverter VCO
+ADF4360-3 (Div by 2)
+Same
+Same
+Same
+Same
+T 56600 26600 5 10 1 1 0 0 1
+date=$Date: 2006/01/09 23:16:07 $
+T 58500 26300 5 10 1 1 0 0 1
+rev=$Revision: 1.14 $
+T 58600 26000 5 10 1 1 0 0 1
+auth=$Author: matt $
+T 54400 26300 5 10 1 1 0 0 1
+fname=$Source: /opt/usrp-hw-cvs/usrp-hw/flex_xcvr/common.sch,v $
+T 57800 27000 8 14 1 1 0 4 1
+title=FlexRF Common
+T 55400 26000 9 10 1 0 0 0 1
+1
+T 56200 26000 9 10 1 0 0 0 1
+3
+C 44400 38200 1 0 0 hmc174ms8.sym
+{
+T 45700 41800 5 10 1 1 0 6 1
+refdes=U202
+}
+C 46900 40900 1 0 0 capacitor-1.sym
+{
+T 47300 41000 5 10 1 1 180 0 1
+refdes=C204
+T 48200 41000 5 10 1 1 180 0 1
+value=220pF
+T 46900 40900 5 10 0 1 270 8 1
+footprint=0603
+}
+N 46500 41100 46900 41100 4
+N 44100 41500 44100 41100 4
+N 44100 41100 44500 41100 4
+N 44000 38400 44000 39100 4
+N 44000 39100 44500 39100 4
+N 44500 38700 44000 38700 4
+T 46400 38600 9 10 1 0 0 0 2
+B high selects  RF1
+A high selects RF2
+C 40800 35100 1 0 0 BNC-1.sym
+{
+T 40800 35900 5 10 1 1 0 0 1
+refdes=J202
+T 40800 35100 5 10 0 1 0 6 1
+footprint=SMA_VERT
+}
+C 40700 34800 1 180 1 generic-power.sym
+{
+T 40900 34550 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 40900 35100 40900 34800 4
+C 43400 35800 1 180 1 capacitor-1.sym
+{
+T 43800 35700 5 10 1 1 180 2 1
+refdes=C206
+T 43800 35400 5 10 1 1 180 2 1
+value=220pF
+T 43400 35800 5 10 0 1 270 2 1
+footprint=0603
+}
+C 43800 33700 1 180 1 generic-power.sym
+{
+T 44000 33450 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 44500 36000 41800 36000 4
+C 44400 33500 1 0 0 hmc174ms8.sym
+{
+T 45700 37100 5 10 1 1 0 6 1
+refdes=U209
+}
+C 46900 36200 1 0 0 capacitor-1.sym
+{
+T 47300 36300 5 10 1 1 180 0 1
+refdes=C205
+T 48200 36300 5 10 1 1 180 0 1
+value=220pF
+T 46900 36200 5 10 0 1 270 8 1
+footprint=0603
+}
+N 46500 36400 46900 36400 4
+N 44100 36800 44100 36400 4
+N 44100 36400 44500 36400 4
+N 44000 33700 44000 34400 4
+N 44000 34400 44500 34400 4
+N 44500 34000 44000 34000 4
+T 46400 33900 9 10 1 0 0 0 2
+B high selects  RF1
+A high selects RF2
+T 52700 41700 9 30 1 0 0 0 1
+TX/RX
+T 40400 35400 9 30 1 0 0 6 1
+RX
+N 49200 36400 47800 36400 4
+{
+T 49000 36400 5 10 1 1 0 6 1
+netname=RF_RX
+}
+N 41300 35600 43400 35600 4
+N 42500 40700 41800 40700 4
+N 41800 36000 41800 40700 4
+N 44300 35600 44500 35600 4
+T 54600 35800 9 10 1 0 0 0 22
+A1	B1	A2	B2
+0	0	0	0		All Off
+
+0	1	0	0		TX Only
+0	1	1	0		TX Only
+
+0	1	0	1		Full Duplex TX and RX
+
+0	0	0	1		RX from secondary RX port
+1	0	0	1		RX from secondary RX port
+1	0	1	0		RX from primary TX/RX port
+
+0	0	1	0		Nothing
+1	0	0	0		Nothing
+
+0	0	1	1		BAD!
+0	1	1	1		BAD!
+1	0	1	1		BAD!
+1	1	0	0		BAD!
+1	1	0	1		BAD!
+1	1	1	0		BAD!
+1	1	1	1		BAD!
+C 41100 31600 1 270 0 resistor-1.sym
+{
+T 41400 31100 5 10 1 1 0 0 1
+value=10K
+T 41100 31600 5 10 0 1 270 0 1
+footprint=0603
+T 41400 30900 5 10 1 1 0 0 1
+refdes=R250
+}
+C 52700 33000 1 90 1 capacitor-1.sym
+{
+T 52900 32900 5 10 1 1 0 6 1
+refdes=C200
+T 52600 32700 5 10 1 1 0 0 1
+value=220pF
+T 52700 33000 5 10 0 1 0 6 1
+footprint=0603
+}
+N 52500 31800 52500 32100 4
+C 55200 33000 1 270 0 capacitor-2.sym
+{
+T 54900 32200 5 10 1 1 0 0 1
+refdes=C208
+T 54900 32000 5 10 1 1 0 0 1
+value=4.7uF
+T 55200 33000 5 10 0 1 0 0 1
+footprint=1206
+}
+C 55800 31500 1 0 0 adp3336.sym
+{
+T 57700 33700 5 10 1 1 0 6 1
+refdes=U203
+}
+N 57900 32400 58100 32400 4
+N 58100 32400 58100 33200 4
+N 58100 32800 57900 32800 4
+C 58100 33700 1 0 0 generic-power.sym
+{
+T 58300 33950 5 10 1 1 0 3 1
+net=3_3V_SW:1
+}
+N 57900 33200 58300 33200 4
+C 53000 33000 1 270 0 capacitor-1.sym
+{
+T 52700 32200 5 10 1 1 0 0 1
+refdes=C203
+T 52700 32000 5 10 1 1 0 0 1
+value=0.1uF
+T 53000 33000 5 10 0 1 0 0 1
+footprint=0603
+}
+C 53900 33000 1 90 1 capacitor-1.sym
+{
+T 54100 32200 5 10 1 1 0 6 1
+refdes=C207
+T 54100 32000 5 10 1 1 0 6 1
+value=1uF
+T 53900 33000 5 10 0 1 0 6 1
+footprint=0603
+}
+N 53700 31800 53700 32100 4
+N 53700 33000 53700 33300 4
+N 53200 31800 53200 32100 4
+N 53200 33000 53200 33300 4
+C 53800 33200 1 0 0 inductor-1.sym
+{
+T 54000 33500 5 10 1 1 0 0 1
+refdes=L202
+T 53800 33200 5 10 0 1 0 0 1
+footprint=1206
+}
+C 54600 33000 1 270 0 capacitor-1.sym
+{
+T 54300 32200 5 10 1 1 0 0 1
+refdes=C209
+T 54300 32000 5 10 1 1 0 0 1
+value=0.1uF
+T 54600 33000 5 10 0 1 0 0 1
+footprint=0603
+}
+N 55400 31800 55400 32100 4
+N 55400 33000 55400 33300 4
+N 54800 31800 54800 32100 4
+N 54800 33000 54800 33300 4
+N 53200 31400 53200 31800 4
+N 54700 33300 55700 33300 4
+N 55700 32800 55900 32800 4
+N 55700 33200 55900 33200 4
+N 55700 32400 55900 32400 4
+N 55700 32400 55700 33300 4
+N 52500 31800 55700 31800 4
+N 55700 31800 55700 32000 4
+N 55700 32000 55900 32000 4
+C 58200 33000 1 270 0 resistor-1.sym
+{
+T 58500 32600 5 10 1 1 180 8 1
+refdes=R201
+T 58200 33000 5 10 0 1 90 8 1
+footprint=0603
+T 58500 32400 5 10 1 1 0 0 1
+value=140K
+}
+C 58200 31900 1 270 0 resistor-1.sym
+{
+T 58500 31500 5 10 1 1 180 8 1
+refdes=R202
+T 58200 31900 5 10 0 1 90 8 1
+footprint=0603
+T 58500 31300 5 10 1 1 0 0 1
+value=78.7K
+}
+N 58300 30900 58300 31000 4
+N 57900 32000 58300 32000 4
+N 58300 31900 58300 32100 4
+N 58300 33000 58300 33700 4
+C 59200 33100 1 90 1 capacitor-1.sym
+{
+T 59100 32800 5 10 1 1 0 0 1
+refdes=C210
+T 59100 32400 5 10 1 1 0 0 1
+value=470pF
+T 59200 33100 5 10 0 1 0 6 1
+footprint=0603
+}
+N 58300 32000 59000 32000 4
+N 59000 32000 59000 32200 4
+N 59000 33200 59000 33100 4
+N 52500 33300 53800 33300 4
+C 53400 31400 1 180 0 generic-power.sym
+{
+T 53200 31150 5 10 1 1 180 3 1
+net=AGND:1
+}
+C 58500 30900 1 180 0 generic-power.sym
+{
+T 58300 30650 5 10 1 1 180 3 1
+net=AGND:1
+}
+C 52700 33600 1 0 1 generic-power.sym
+{
+T 52500 33850 5 10 1 1 180 5 1
+net=6V_RX:1
+}
+N 52500 33000 52500 33600 4
+C 43900 41500 1 0 0 generic-power.sym
+{
+T 44100 41750 5 10 1 1 0 3 1
+net=3_3V_SW:1
+}
+C 43900 36800 1 0 0 generic-power.sym
+{
+T 44100 37050 5 10 1 1 0 3 1
+net=3_3V_SW:1
+}
+C 44800 29500 1 0 0 7404-3.sym
+{
+T 46300 31500 5 10 1 1 0 0 1
+refdes=U204
+T 45200 29300 5 10 1 1 0 0 1
+net=3_3V_SW:14
+T 45200 29100 5 10 1 1 0 0 1
+net=AGND:7
+T 44800 29500 5 10 0 1 0 0 1
+footprint=SO14
+}
+N 46800 30600 48200 30600 4
+{
+T 47300 30600 5 10 1 1 0 0 1
+netname=TX
+}
+N 46800 30300 48200 30300 4
+{
+T 47300 30300 5 10 1 1 0 0 1
+netname=RX
+}
+N 46800 30000 48200 30000 4
+{
+T 47300 30000 5 10 1 1 0 0 1
+netname=RX1
+}
+N 46800 29700 48200 29700 4
+{
+T 47300 29700 5 10 1 1 0 0 1
+netname=RX2
+}
+N 43100 39500 44500 39500 4
+{
+T 43600 39500 5 10 1 1 0 0 1
+netname=TX
+}
+N 43100 39900 44500 39900 4
+{
+T 43600 39900 5 10 1 1 0 0 1
+netname=RX
+}
+N 43100 35200 44500 35200 4
+{
+T 43600 35200 5 10 1 1 0 0 1
+netname=RX1
+}
+N 43100 34800 44500 34800 4
+{
+T 43600 34800 5 10 1 1 0 0 1
+netname=RX2
+}
+N 41200 29700 44800 29700 4
+{
+T 41700 29700 5 10 1 1 0 0 1
+netname=RX1
+}
+N 41200 30300 44800 30300 4
+{
+T 41700 30300 5 10 1 1 0 0 1
+netname=TX
+}
+N 41200 30600 41200 30700 4
+C 41000 32100 1 0 0 generic-power.sym
+{
+T 41200 32350 5 10 1 1 0 3 1
+net=3_3V_SW:1
+}
+N 41200 31600 41200 32100 4
+C 41000 31600 1 90 1 resistor-1.sym
+{
+T 40700 31100 5 10 1 1 0 6 1
+value=10K
+T 41000 31600 5 10 0 1 270 2 1
+footprint=0603
+T 40700 30900 5 10 1 1 0 6 1
+refdes=R249
+}
+N 41200 31900 40900 31900 4
+N 40900 31900 40900 31600 4
+N 40900 30700 40900 30000 4
+N 40900 30000 44800 30000 4
+{
+T 41500 30000 5 10 1 1 0 0 1
+netname=io_rx_06
+}
+N 41200 31900 42200 31900 4
+N 42200 31900 42200 30900 4
+T 53700 34400 9 25 1 0 0 0 1
+Always On
+C 49400 39900 1 90 0 capacitor-1.sym
+{
+T 49300 40500 5 10 1 1 0 0 1
+refdes=C221
+T 49300 40100 5 10 1 1 0 0 1
+value=C221
+T 49400 39900 5 10 0 1 0 8 1
+footprint=0603
+}
+C 49000 39900 1 90 0 inductor-1.sym
+{
+T 48400 40500 5 10 1 1 0 0 1
+refdes=L221
+T 49000 39900 5 10 0 1 90 0 1
+footprint=0603
+T 48800 40200 5 10 1 1 0 6 1
+value=L221
+}
+N 48900 39900 48900 39800 4
+N 48900 39800 49200 39800 4
+N 48900 40800 48900 40900 4
+N 48900 40900 49200 40900 4
+N 49200 40900 49200 40800 4
+C 51000 39900 1 90 0 capacitor-1.sym
+{
+T 50900 40500 5 10 1 1 0 0 1
+refdes=C222
+T 50900 40100 5 10 1 1 0 0 1
+value=C222
+T 51000 39900 5 10 0 1 0 8 1
+footprint=0603
+}
+C 50600 39900 1 90 0 inductor-1.sym
+{
+T 49900 40500 5 10 1 1 0 0 1
+refdes=L222
+T 50600 39900 5 10 0 1 90 0 1
+footprint=0603
+T 50400 40200 5 10 1 1 0 6 1
+value=L222
+}
+N 50500 39900 50500 39800 4
+N 50500 39800 50800 39800 4
+N 50800 39800 50800 39900 4
+N 50500 40800 50500 40900 4
+N 50500 40900 50800 40900 4
+N 50800 40900 50800 40800 4
+C 52600 39900 1 90 0 capacitor-1.sym
+{
+T 52500 40500 5 10 1 1 0 0 1
+refdes=C223
+T 52500 40100 5 10 1 1 0 0 1
+value=C223
+T 52600 39900 5 10 0 1 0 8 1
+footprint=0603
+}
+C 52200 39900 1 90 0 inductor-1.sym
+{
+T 51500 40500 5 10 1 1 0 0 1
+refdes=L223
+T 52200 39900 5 10 0 1 90 0 1
+footprint=0603
+T 52000 40200 5 10 1 1 0 6 1
+value=L223
+}
+N 52100 39800 52400 39800 4
+N 52400 39800 52400 39900 4
+N 52100 40800 52100 40900 4
+N 52100 40900 52400 40900 4
+N 52400 40900 52400 40800 4
+C 49400 40800 1 0 0 capacitor-1.sym
+{
+T 49900 41100 5 10 1 1 0 0 1
+refdes=C224
+T 49400 41100 5 10 1 1 0 0 1
+value=C224
+T 49400 40800 5 10 0 1 270 8 1
+footprint=0603
+}
+C 49400 41200 1 0 0 inductor-1.sym
+{
+T 49900 41400 5 10 1 1 0 0 1
+refdes=L224
+T 49400 41200 5 10 0 1 0 0 1
+footprint=0603
+T 49400 41400 5 10 1 1 0 0 1
+value=L224
+}
+N 49400 41300 49300 41300 4
+N 49300 41300 49300 41000 4
+N 49300 41000 49400 41000 4
+N 50300 41300 50400 41300 4
+N 50400 41300 50400 41000 4
+N 50400 41000 50300 41000 4
+C 51000 40800 1 0 0 capacitor-1.sym
+{
+T 51500 41100 5 10 1 1 0 0 1
+refdes=C225
+T 51000 41100 5 10 1 1 0 0 1
+value=C225
+T 51000 40800 5 10 0 1 270 8 1
+footprint=0603
+}
+C 51000 41200 1 0 0 inductor-1.sym
+{
+T 51500 41400 5 10 1 1 0 0 1
+refdes=L225
+T 51000 41200 5 10 0 1 0 0 1
+footprint=0603
+T 51000 41400 5 10 1 1 0 0 1
+value=L225
+}
+N 51000 41300 50900 41300 4
+N 50900 41300 50900 41000 4
+N 50900 41000 51000 41000 4
+N 51900 41300 52000 41300 4
+N 52000 41300 52000 41000 4
+N 52000 41000 51900 41000 4
+N 47800 41100 49300 41100 4
+N 50400 41100 50900 41100 4
+N 52000 41100 53400 41100 4
+N 52300 41100 52300 40900 4
+N 50700 41100 50700 40900 4
+N 49100 41100 49100 40900 4
+C 50700 39300 1 180 0 generic-power.sym
+{
+T 50500 39050 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 49200 39500 49200 39900 4
+N 49200 39500 52100 39500 4
+N 52100 39500 52100 39900 4
+N 50700 39800 50700 39500 4
+N 50500 39500 50500 39300 4
+C 60300 33100 1 90 1 capacitor-1.sym
+{
+T 60200 32800 5 10 1 1 0 0 1
+refdes=C240
+T 60200 32400 5 10 1 1 0 0 1
+value=1uF
+T 60300 33100 5 10 0 1 0 6 1
+footprint=0603
+}
+N 58300 33200 60100 33200 4
+N 60100 33200 60100 33100 4
+N 60100 32100 60100 32200 4
+C 60300 32100 1 180 0 generic-power.sym
+{
+T 60100 31850 5 10 1 1 180 3 1
+net=AGND:1
+}
+C 700 6000 1 0 0 saw0900-SAWTEK856327.sym
+{
+T 52100 36100 5 10 1 1 0 6 1
+refdes=FIL2
+T 52200 35900 5 10 1 1 0 0 1
+value=FIL2
+}
+C 700 8400 1 0 0 saw2400-SAWTEK855916.sym
+{
+T 52100 38500 5 10 1 1 0 6 1
+refdes=FIL1
+T 52200 38200 5 10 1 1 0 0 1
+value=FIL1
+}
+C 51700 34700 1 180 0 generic-power.sym
+{
+T 51500 34450 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 51500 34900 51500 34700 4
+N 51300 34900 51300 34800 4
+N 51300 34800 51500 34800 4
+C 51700 37100 1 180 0 generic-power.sym
+{
+T 51500 36850 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 51500 37300 51500 37100 4
+N 51300 37300 51300 37200 4
+N 51100 37300 51100 37200 4
+N 51100 37200 51500 37200 4
+N 51500 37200 51700 37200 4
+N 51700 37200 51700 37300 4
+N 53000 38000 52300 38000 4
+N 53000 35600 53000 41100 4
+N 53000 35600 52300 35600 4
+N 48300 41100 48300 38000 4
+N 48300 38000 50400 38000 4
+N 49800 38000 49800 35600 4
+N 49800 35600 50400 35600 4
+N 44800 30900 43700 30900 4
+{
+T 43900 30900 5 10 1 1 0 0 1
+netname=io_rx_07
+}
+C 42800 30800 1 0 0 resistor-1.sym
+{
+T 42900 30600 5 10 1 1 180 8 1
+refdes=R262
+T 42800 30800 5 10 0 1 180 8 1
+footprint=0603
+T 43300 30600 5 10 1 1 0 0 1
+value=3.32K
+}
+C 42700 31300 1 180 1 resistor-1.sym
+{
+T 42700 31500 5 10 1 1 0 2 1
+refdes=R261
+T 42700 31300 5 10 0 1 0 2 1
+footprint=0603
+T 43200 31500 5 10 1 1 180 6 1
+value=3.32K
+}
+N 44800 31200 43600 31200 4
+{
+T 43900 31200 5 10 1 1 0 0 1
+netname=io_tx_07
+}
+N 42200 30900 42800 30900 4
+N 42700 31200 42200 31200 4
+N 46800 31200 48200 31200 4
+{
+T 47200 31200 5 10 1 1 0 0 1
+netname=TX_PUP
+}
+N 46800 30900 48200 30900 4
+{
+T 47200 30900 5 10 1 1 0 0 1
+netname=RX_PUP
+}
diff --git a/usrp-hw/rfx/common2400.sch b/usrp-hw/rfx/common2400.sch
new file mode 100644
index 000000000..3fcda52d7
--- /dev/null
+++ b/usrp-hw/rfx/common2400.sch
@@ -0,0 +1,538 @@
+v 20050820 1
+C 39500 25900 0 0 0 title-C.sym
+C 52000 40600 1 0 1 BNC-1.sym
+{
+T 52000 41400 5 10 1 1 0 6 1
+refdes=J200
+T 52000 40600 5 10 0 1 0 0 1
+footprint=SMA_VERT
+}
+C 52100 40300 1 180 0 generic-power.sym
+{
+T 51900 40050 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 51900 40600 51900 40300 4
+C 44000 40500 1 180 0 capacitor-1.sym
+{
+T 43700 40400 5 10 1 1 0 0 1
+refdes=C201
+T 44400 40100 5 10 1 1 0 6 1
+value=100pF
+T 44000 40500 5 10 0 1 270 0 1
+footprint=0603
+}
+C 42500 40900 1 180 1 capacitor-1.sym
+{
+T 42900 40800 5 10 1 1 180 2 1
+refdes=C202
+T 42900 40500 5 10 1 1 180 2 1
+value=100pF
+T 42500 40900 5 10 0 1 270 2 1
+footprint=0603
+}
+C 43800 38400 1 180 1 generic-power.sym
+{
+T 44000 38150 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 44000 40300 44500 40300 4
+N 44500 40700 43400 40700 4
+N 43100 40300 42000 40300 4
+{
+T 42100 40300 5 10 1 1 0 0 1
+netname=RF_TX
+}
+N 41200 30600 44800 30600 4
+{
+T 41500 30600 5 10 1 1 0 0 1
+netname=io_tx_06
+}
+T 40300 26300 9 15 1 0 0 0 6
+Band
+400 - 500 MHz
+800 - 975 MHz
+1.2 - 1.3 GHz
+2.3 - 2.4 GHz
+2.4 - 2.7 GHz
+T 47100 26300 9 15 1 0 0 0 6
+Upconverter VCO
+ADF4360-7 (Div by 2)
+ADF4360-3 (Div by 2)
+ADF4360-0 (Div by 2)
+ADF4360-1
+ADF4360-0
+T 42900 26300 9 15 1 0 0 0 6
+Upconverter
+AD8345
+AD8349
+AD8349
+AD8349
+AD8349
+T 44900 26300 9 15 1 0 0 0 6
+Downconverter
+AD8348
+AD8347
+AD8347
+AD8347
+AD8347
+T 50300 26300 9 15 1 0 0 0 6
+Downconverter VCO
+ADF4360-3 (Div by 2)
+Same
+Same
+Same
+Same
+T 56600 26600 5 10 1 1 0 0 1
+date=$Date: 2006/03/10 02:20:13 $
+T 58500 26300 5 10 1 1 0 0 1
+rev=$Revision: 1.2 $
+T 58600 26000 5 10 1 1 0 0 1
+auth=$Author: matt $
+T 54400 26300 5 10 1 1 0 0 1
+fname=$Source: /opt/usrp-hw-cvs/usrp-hw/flex_xcvr/common2400.sch,v $
+T 57800 27000 8 14 1 1 0 4 1
+title=Flex2400 Common
+T 55400 26000 9 10 1 0 0 0 1
+1
+T 56200 26000 9 10 1 0 0 0 1
+3
+C 44400 38200 1 0 0 hmc174ms8.sym
+{
+T 45700 41800 5 10 1 1 0 6 1
+refdes=U202
+}
+C 48800 40900 1 0 0 capacitor-1.sym
+{
+T 49200 41000 5 10 1 1 180 0 1
+refdes=C204
+T 50100 41000 5 10 1 1 180 0 1
+value=NONE
+T 48800 40900 5 10 0 1 270 8 1
+footprint=0603
+}
+N 46500 41100 48800 41100 4
+N 44100 41500 44100 41100 4
+N 44100 41100 44500 41100 4
+N 44000 38400 44000 39100 4
+N 44000 39100 44500 39100 4
+N 44500 38700 44000 38700 4
+T 46400 38600 9 10 1 0 0 0 2
+B high selects  RF1
+A high selects RF2
+C 40800 35100 1 0 0 BNC-1.sym
+{
+T 40800 35900 5 10 1 1 0 0 1
+refdes=J202
+T 40800 35100 5 10 0 1 0 6 1
+footprint=SMA_VERT
+}
+C 40700 34800 1 180 1 generic-power.sym
+{
+T 40900 34550 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 40900 35100 40900 34800 4
+C 43400 35800 1 180 1 capacitor-1.sym
+{
+T 43800 35700 5 10 1 1 180 2 1
+refdes=C206
+T 43800 35400 5 10 1 1 180 2 1
+value=100pF
+T 43400 35800 5 10 0 1 270 2 1
+footprint=0603
+}
+C 43800 33700 1 180 1 generic-power.sym
+{
+T 44000 33450 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 44500 36000 41800 36000 4
+C 44400 33500 1 0 0 hmc174ms8.sym
+{
+T 45700 37100 5 10 1 1 0 6 1
+refdes=U209
+}
+C 46900 36200 1 0 0 capacitor-1.sym
+{
+T 47300 36300 5 10 1 1 180 0 1
+refdes=C205
+T 48200 36300 5 10 1 1 180 0 1
+value=100pF
+T 46900 36200 5 10 0 1 270 8 1
+footprint=0603
+}
+N 46500 36400 46900 36400 4
+N 44100 36800 44100 36400 4
+N 44100 36400 44500 36400 4
+N 44000 33700 44000 34400 4
+N 44000 34400 44500 34400 4
+N 44500 34000 44000 34000 4
+T 46400 33900 9 10 1 0 0 0 2
+B high selects  RF1
+A high selects RF2
+T 50800 41700 9 30 1 0 0 0 1
+TX/RX
+T 40400 35400 9 30 1 0 0 6 1
+RX
+N 49200 36400 47800 36400 4
+{
+T 49000 36400 5 10 1 1 0 6 1
+netname=RF_RX
+}
+N 41300 35600 43400 35600 4
+N 42500 40700 41800 40700 4
+N 41800 36000 41800 40700 4
+N 44300 35600 44500 35600 4
+T 54600 35800 9 10 1 0 0 0 22
+A1	B1	A2	B2
+0	0	0	0		All Off
+
+0	1	0	0		TX Only
+0	1	1	0		TX Only
+
+0	1	0	1		Full Duplex TX and RX
+
+0	0	0	1		RX from secondary RX port
+1	0	0	1		RX from secondary RX port
+1	0	1	0		RX from primary TX/RX port
+
+0	0	1	0		Nothing
+1	0	0	0		Nothing
+
+0	0	1	1		BAD!
+0	1	1	1		BAD!
+1	0	1	1		BAD!
+1	1	0	0		BAD!
+1	1	0	1		BAD!
+1	1	1	0		BAD!
+1	1	1	1		BAD!
+C 41100 31600 1 270 0 resistor-1.sym
+{
+T 41400 31100 5 10 1 1 0 0 1
+value=10K
+T 41100 31600 5 10 0 1 270 0 1
+footprint=0603
+T 41400 30900 5 10 1 1 0 0 1
+refdes=R250
+}
+C 52700 33000 1 90 1 capacitor-1.sym
+{
+T 52900 32900 5 10 1 1 0 6 1
+refdes=C200
+T 52600 32700 5 10 1 1 0 0 1
+value=220pF
+T 52700 33000 5 10 0 1 0 6 1
+footprint=0603
+}
+N 52500 31800 52500 32100 4
+C 55200 33000 1 270 0 capacitor-2.sym
+{
+T 54900 32200 5 10 1 1 0 0 1
+refdes=C208
+T 54900 32000 5 10 1 1 0 0 1
+value=4.7uF
+T 55200 33000 5 10 0 1 0 0 1
+footprint=1206
+}
+C 55800 31500 1 0 0 adp3336.sym
+{
+T 57700 33700 5 10 1 1 0 6 1
+refdes=U203
+}
+N 57900 32400 58100 32400 4
+N 58100 32400 58100 33200 4
+N 58100 32800 57900 32800 4
+C 58100 33700 1 0 0 generic-power.sym
+{
+T 58300 33950 5 10 1 1 0 3 1
+net=3_3V_SW:1
+}
+N 57900 33200 58300 33200 4
+C 53000 33000 1 270 0 capacitor-1.sym
+{
+T 52700 32200 5 10 1 1 0 0 1
+refdes=C203
+T 52700 32000 5 10 1 1 0 0 1
+value=0.1uF
+T 53000 33000 5 10 0 1 0 0 1
+footprint=0603
+}
+C 53900 33000 1 90 1 capacitor-1.sym
+{
+T 54100 32200 5 10 1 1 0 6 1
+refdes=C207
+T 54100 32000 5 10 1 1 0 6 1
+value=1uF
+T 53900 33000 5 10 0 1 0 6 1
+footprint=0603
+}
+N 53700 31800 53700 32100 4
+N 53700 33000 53700 33300 4
+N 53200 31800 53200 32100 4
+N 53200 33000 53200 33300 4
+C 53800 33200 1 0 0 inductor-1.sym
+{
+T 54000 33500 5 10 1 1 0 0 1
+refdes=L202
+T 53800 33200 5 10 0 1 0 0 1
+footprint=1206
+}
+C 54600 33000 1 270 0 capacitor-1.sym
+{
+T 54300 32200 5 10 1 1 0 0 1
+refdes=C209
+T 54300 32000 5 10 1 1 0 0 1
+value=0.1uF
+T 54600 33000 5 10 0 1 0 0 1
+footprint=0603
+}
+N 55400 31800 55400 32100 4
+N 55400 33000 55400 33300 4
+N 54800 31800 54800 32100 4
+N 54800 33000 54800 33300 4
+N 53200 31400 53200 31800 4
+N 54700 33300 55700 33300 4
+N 55700 32800 55900 32800 4
+N 55700 33200 55900 33200 4
+N 55700 32400 55900 32400 4
+N 55700 32400 55700 33300 4
+N 52500 31800 55700 31800 4
+N 55700 31800 55700 32000 4
+N 55700 32000 55900 32000 4
+C 58200 33000 1 270 0 resistor-1.sym
+{
+T 58500 32600 5 10 1 1 180 8 1
+refdes=R201
+T 58200 33000 5 10 0 1 90 8 1
+footprint=0603
+T 58500 32400 5 10 1 1 0 0 1
+value=140K
+}
+C 58200 31900 1 270 0 resistor-1.sym
+{
+T 58500 31500 5 10 1 1 180 8 1
+refdes=R202
+T 58200 31900 5 10 0 1 90 8 1
+footprint=0603
+T 58500 31300 5 10 1 1 0 0 1
+value=78.7K
+}
+N 58300 30900 58300 31000 4
+N 57900 32000 58300 32000 4
+N 58300 31900 58300 32100 4
+N 58300 33000 58300 33700 4
+C 59200 33100 1 90 1 capacitor-1.sym
+{
+T 59100 32800 5 10 1 1 0 0 1
+refdes=C210
+T 59100 32400 5 10 1 1 0 0 1
+value=470pF
+T 59200 33100 5 10 0 1 0 6 1
+footprint=0603
+}
+N 58300 32000 59000 32000 4
+N 59000 32000 59000 32200 4
+N 59000 33200 59000 33100 4
+N 52500 33300 53800 33300 4
+C 53400 31400 1 180 0 generic-power.sym
+{
+T 53200 31150 5 10 1 1 180 3 1
+net=AGND:1
+}
+C 58500 30900 1 180 0 generic-power.sym
+{
+T 58300 30650 5 10 1 1 180 3 1
+net=AGND:1
+}
+C 52700 33600 1 0 1 generic-power.sym
+{
+T 52500 33850 5 10 1 1 180 5 1
+net=6V_RX:1
+}
+N 52500 33000 52500 33600 4
+C 43900 41500 1 0 0 generic-power.sym
+{
+T 44100 41750 5 10 1 1 0 3 1
+net=3_3V_SW:1
+}
+C 43900 36800 1 0 0 generic-power.sym
+{
+T 44100 37050 5 10 1 1 0 3 1
+net=3_3V_SW:1
+}
+C 44800 29500 1 0 0 7404-3.sym
+{
+T 46300 31500 5 10 1 1 0 0 1
+refdes=U204
+T 45200 29300 5 10 1 1 0 0 1
+net=3_3V_SW:14
+T 45200 29100 5 10 1 1 0 0 1
+net=AGND:7
+T 44800 29500 5 10 0 1 0 0 1
+footprint=SO14
+}
+N 46800 30600 48200 30600 4
+{
+T 47300 30600 5 10 1 1 0 0 1
+netname=TX
+}
+N 46800 30300 48200 30300 4
+{
+T 47300 30300 5 10 1 1 0 0 1
+netname=RX
+}
+N 46800 30000 48200 30000 4
+{
+T 47300 30000 5 10 1 1 0 0 1
+netname=RX1
+}
+N 46800 29700 48200 29700 4
+{
+T 47300 29700 5 10 1 1 0 0 1
+netname=RX2
+}
+N 43100 39500 44500 39500 4
+{
+T 43600 39500 5 10 1 1 0 0 1
+netname=TX
+}
+N 43100 39900 44500 39900 4
+{
+T 43600 39900 5 10 1 1 0 0 1
+netname=RX
+}
+N 43100 35200 44500 35200 4
+{
+T 43600 35200 5 10 1 1 0 0 1
+netname=RX1
+}
+N 43100 34800 44500 34800 4
+{
+T 43600 34800 5 10 1 1 0 0 1
+netname=RX2
+}
+N 41200 29700 44800 29700 4
+{
+T 41700 29700 5 10 1 1 0 0 1
+netname=RX1
+}
+N 41200 30300 44800 30300 4
+{
+T 41700 30300 5 10 1 1 0 0 1
+netname=TX
+}
+N 41200 30600 41200 30700 4
+C 41000 32100 1 0 0 generic-power.sym
+{
+T 41200 32350 5 10 1 1 0 3 1
+net=3_3V_SW:1
+}
+N 41200 31600 41200 32100 4
+C 41000 31600 1 90 1 resistor-1.sym
+{
+T 40700 31100 5 10 1 1 0 6 1
+value=10K
+T 41000 31600 5 10 0 1 270 2 1
+footprint=0603
+T 40700 30900 5 10 1 1 0 6 1
+refdes=R249
+}
+N 41200 31900 40900 31900 4
+N 40900 31900 40900 31600 4
+N 40900 30700 40900 30000 4
+N 40900 30000 44800 30000 4
+{
+T 41500 30000 5 10 1 1 0 0 1
+netname=io_rx_06
+}
+T 53700 34400 9 25 1 0 0 0 1
+Always On
+N 49700 41100 51500 41100 4
+C 60300 33100 1 90 1 capacitor-1.sym
+{
+T 60200 32800 5 10 1 1 0 0 1
+refdes=C240
+T 60200 32400 5 10 1 1 0 0 1
+value=1uF
+T 60300 33100 5 10 0 1 0 6 1
+footprint=0603
+}
+N 58300 33200 60100 33200 4
+N 60100 33200 60100 33100 4
+N 60100 32100 60100 32200 4
+C 60300 32100 1 180 0 generic-power.sym
+{
+T 60100 31850 5 10 1 1 180 3 1
+net=AGND:1
+}
+C -1200 8400 1 0 0 saw2400-SAWTEK855916.sym
+{
+T 50200 38500 5 10 1 1 0 6 1
+refdes=FIL1
+T 50300 38200 5 10 1 1 0 0 1
+value=FIL1
+}
+C 49800 37100 1 180 0 generic-power.sym
+{
+T 49600 36850 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 49600 37300 49600 37100 4
+N 49400 37300 49400 37200 4
+N 49200 37300 49200 37200 4
+N 49200 37200 49600 37200 4
+N 49600 37200 49800 37200 4
+N 49800 37200 49800 37300 4
+N 51100 38000 50400 38000 4
+N 51100 38000 51100 41100 4
+N 46700 41100 46700 38000 4
+N 46700 38000 48500 38000 4
+N 44800 30900 43700 30900 4
+{
+T 43900 30900 5 10 1 1 0 0 1
+netname=io_rx_07
+}
+C 42800 30800 1 0 0 resistor-1.sym
+{
+T 42900 30600 5 10 1 1 180 8 1
+refdes=R262
+T 42800 30800 5 10 0 1 180 8 1
+footprint=0603
+T 43300 30600 5 10 1 1 0 0 1
+value=3.32K
+}
+C 42700 31300 1 180 1 resistor-1.sym
+{
+T 42700 31500 5 10 1 1 0 2 1
+refdes=R261
+T 42700 31300 5 10 0 1 0 2 1
+footprint=0603
+T 43200 31500 5 10 1 1 180 6 1
+value=3.32K
+}
+N 44800 31200 43600 31200 4
+{
+T 43900 31200 5 10 1 1 0 0 1
+netname=io_tx_07
+}
+N 42200 30900 42800 30900 4
+N 42700 31200 42200 31200 4
+N 46800 31200 48200 31200 4
+{
+T 47200 31200 5 10 1 1 0 0 1
+netname=TX_PUP
+}
+N 46800 30900 48200 30900 4
+{
+T 47200 30900 5 10 1 1 0 0 1
+netname=RX_PUP
+}
+C 42500 32000 1 180 1 generic-power.sym
+{
+T 42700 31750 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 42200 30900 42200 32100 4
+N 42200 32100 42700 32100 4
+N 42700 32100 42700 32000 4
diff --git a/usrp-hw/rfx/common400.sch b/usrp-hw/rfx/common400.sch
new file mode 100644
index 000000000..2389104c0
--- /dev/null
+++ b/usrp-hw/rfx/common400.sch
@@ -0,0 +1,609 @@
+v 20050820 1
+C 39500 25900 0 0 0 title-C.sym
+T 55500 28900 9 10 1 0 0 0 1
+Band Filter
+C 53900 40600 1 0 1 BNC-1.sym
+{
+T 53900 41400 5 10 1 1 0 6 1
+refdes=J200
+T 53900 40600 5 10 0 1 0 0 1
+footprint=SMA_VERT
+}
+C 54000 40300 1 180 0 generic-power.sym
+{
+T 53800 40050 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 53800 40600 53800 40300 4
+C 44000 40500 1 180 0 capacitor-1.sym
+{
+T 43700 40400 5 10 1 1 0 0 1
+refdes=C201
+T 44400 40100 5 10 1 1 0 6 1
+value=1000pF
+T 44000 40500 5 10 0 1 270 0 1
+footprint=0603
+}
+T 55500 28700 9 10 1 0 0 0 1
+Exposed paddle on Quad Mod
+C 42500 40900 1 180 1 capacitor-1.sym
+{
+T 42900 40800 5 10 1 1 180 2 1
+refdes=C202
+T 42900 40500 5 10 1 1 180 2 1
+value=1000pF
+T 42500 40900 5 10 0 1 270 2 1
+footprint=0603
+}
+C 43800 38400 1 180 1 generic-power.sym
+{
+T 44000 38150 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 44000 40300 44500 40300 4
+N 44500 40700 43400 40700 4
+N 43100 40300 42000 40300 4
+{
+T 42100 40300 5 10 1 1 0 0 1
+netname=RF_TX
+}
+N 41200 30600 42600 30600 4
+{
+T 41500 30600 5 10 1 1 0 0 1
+netname=io_tx_06
+}
+T 40300 26300 9 15 1 0 0 0 6
+Band
+400 - 500 MHz
+800 - 975 MHz
+1.2 - 1.3 GHz
+2.3 - 2.4 GHz
+2.4 - 2.7 GHz
+T 47100 26300 9 15 1 0 0 0 6
+Upconverter VCO
+ADF4360-7 (Div by 2)
+ADF4360-3 (Div by 2)
+ADF4360-0 (Div by 2)
+ADF4360-1
+ADF4360-0
+T 42900 26300 9 15 1 0 0 0 6
+Upconverter
+AD8345
+AD8349
+AD8349
+AD8349
+AD8349
+T 44900 26300 9 15 1 0 0 0 6
+Downconverter
+AD8348
+AD8347
+AD8347
+AD8347
+AD8347
+T 50300 26300 9 15 1 0 0 0 6
+Downconverter VCO
+ADF4360-3 (Div by 2)
+Same
+Same
+Same
+Same
+T 56600 26600 5 10 1 1 0 0 1
+date=$Date: 2005/12/13 20:27:08 $
+T 58500 26300 5 10 1 1 0 0 1
+rev=$Revision: 1.13 $
+T 58600 26000 5 10 1 1 0 0 1
+auth=$Author: matt $
+T 54400 26300 5 10 1 1 0 0 1
+fname=$Source: /opt/usrp-hw-cvs/usrp-hw/flex_xcvr/common400.sch,v $
+T 57800 27000 8 14 1 1 0 4 1
+title=Flex400 Common
+T 55400 26000 9 10 1 0 0 0 1
+1
+T 56200 26000 9 10 1 0 0 0 1
+3
+C 44400 38200 1 0 0 hmc174ms8.sym
+{
+T 46500 41600 5 10 1 1 0 6 1
+refdes=U202
+}
+C 46900 40900 1 0 0 capacitor-1.sym
+{
+T 47300 41000 5 10 1 1 180 0 1
+refdes=C204
+T 48200 41000 5 10 1 1 180 0 1
+value=1000pF
+T 46900 40900 5 10 0 1 270 8 1
+footprint=0603
+}
+N 46500 41100 46900 41100 4
+N 44100 41500 44100 41100 4
+N 44100 41100 44500 41100 4
+N 44000 38400 44000 39100 4
+N 44000 39100 44500 39100 4
+N 44500 38700 44000 38700 4
+T 46400 38600 9 10 1 0 0 0 2
+B high selects  RF1
+A high selects RF2
+C 40800 35100 1 0 0 BNC-1.sym
+{
+T 40800 35900 5 10 1 1 0 0 1
+refdes=J202
+T 40800 35100 5 10 0 1 0 6 1
+footprint=SMA_VERT
+}
+C 40700 34800 1 180 1 generic-power.sym
+{
+T 40900 34550 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 40900 35100 40900 34800 4
+C 43400 35800 1 180 1 capacitor-1.sym
+{
+T 43800 35700 5 10 1 1 180 2 1
+refdes=C206
+T 43800 35400 5 10 1 1 180 2 1
+value=1000pF
+T 43400 35800 5 10 0 1 270 2 1
+footprint=0603
+}
+C 43800 33700 1 180 1 generic-power.sym
+{
+T 44000 33450 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 44500 36000 41800 36000 4
+C 44400 33500 1 0 0 hmc174ms8.sym
+{
+T 46500 36900 5 10 1 1 0 6 1
+refdes=U209
+}
+C 46900 36200 1 0 0 capacitor-1.sym
+{
+T 47300 36300 5 10 1 1 180 0 1
+refdes=C205
+T 48200 36300 5 10 1 1 180 0 1
+value=1000pF
+T 46900 36200 5 10 0 1 270 8 1
+footprint=0603
+}
+N 46500 36400 46900 36400 4
+N 44100 36800 44100 36400 4
+N 44100 36400 44500 36400 4
+N 44000 33700 44000 34400 4
+N 44000 34400 44500 34400 4
+N 44500 34000 44000 34000 4
+T 46400 33900 9 10 1 0 0 0 2
+B high selects  RF1
+A high selects RF2
+T 52700 41700 9 30 1 0 0 0 1
+TX/RX
+T 40400 35400 9 30 1 0 0 6 1
+RX
+N 49200 36400 47800 36400 4
+{
+T 49000 36400 5 10 1 1 0 6 1
+netname=RF_RX
+}
+N 41300 35600 43400 35600 4
+N 42500 40700 41800 40700 4
+N 41800 36000 41800 40700 4
+N 44300 35600 44500 35600 4
+T 54600 35800 9 10 1 0 0 0 22
+A1	B1	A2	B2
+0	0	0	0		All Off
+
+0	1	0	0		TX Only
+0	1	1	0		TX Only
+
+0	1	0	1		Full Duplex TX and RX
+
+0	0	0	1		RX from secondary RX port
+1	0	0	1		RX from secondary RX port
+1	0	1	0		RX from primary TX/RX port
+
+0	0	1	0		Nothing
+1	0	0	0		Nothing
+
+0	0	1	1		BAD!
+0	1	1	1		BAD!
+1	0	1	1		BAD!
+1	1	0	0		BAD!
+1	1	0	1		BAD!
+1	1	1	0		BAD!
+1	1	1	1		BAD!
+C 41100 31600 1 270 0 resistor-1.sym
+{
+T 41400 31100 5 10 1 1 0 0 1
+value=10K
+T 41100 31600 5 10 0 1 270 0 1
+footprint=0603
+T 41400 30900 5 10 1 1 0 0 1
+refdes=R250
+}
+C 52700 33000 1 90 1 capacitor-1.sym
+{
+T 52900 32900 5 10 1 1 0 6 1
+refdes=C200
+T 52600 32700 5 10 1 1 0 0 1
+value=220pF
+T 52700 33000 5 10 0 1 0 6 1
+footprint=0603
+}
+N 52500 31800 52500 32100 4
+C 55200 33000 1 270 0 capacitor-2.sym
+{
+T 54900 32200 5 10 1 1 0 0 1
+refdes=C208
+T 54900 32000 5 10 1 1 0 0 1
+value=4.7uF
+T 55200 33000 5 10 0 1 0 0 1
+footprint=1206
+}
+C 55800 31500 1 0 0 adp3336.sym
+{
+T 57600 33700 5 10 1 1 0 6 1
+refdes=U203
+}
+N 57900 32400 58100 32400 4
+N 58100 32400 58100 33200 4
+N 58100 32800 57900 32800 4
+C 58100 33700 1 0 0 generic-power.sym
+{
+T 58300 33950 5 10 1 1 0 3 1
+net=3_3V_SW:1
+}
+N 57900 33200 58300 33200 4
+C 53000 33000 1 270 0 capacitor-1.sym
+{
+T 52700 32200 5 10 1 1 0 0 1
+refdes=C203
+T 52700 32000 5 10 1 1 0 0 1
+value=0.1uF
+T 53000 33000 5 10 0 1 0 0 1
+footprint=0603
+}
+C 53900 33000 1 90 1 capacitor-1.sym
+{
+T 54100 32200 5 10 1 1 0 6 1
+refdes=C207
+T 54100 32000 5 10 1 1 0 6 1
+value=1uF
+T 53900 33000 5 10 0 1 0 6 1
+footprint=0603
+}
+N 53700 31800 53700 32100 4
+N 53700 33000 53700 33300 4
+N 53200 31800 53200 32100 4
+N 53200 33000 53200 33300 4
+C 53800 33200 1 0 0 inductor-1.sym
+{
+T 54000 33500 5 10 1 1 0 0 1
+refdes=L202
+T 53800 33200 5 10 0 1 0 0 1
+footprint=1206
+}
+C 54600 33000 1 270 0 capacitor-1.sym
+{
+T 54300 32200 5 10 1 1 0 0 1
+refdes=C209
+T 54300 32000 5 10 1 1 0 0 1
+value=0.1uF
+T 54600 33000 5 10 0 1 0 0 1
+footprint=0603
+}
+N 55400 31800 55400 32100 4
+N 55400 33000 55400 33300 4
+N 54800 31800 54800 32100 4
+N 54800 33000 54800 33300 4
+N 53200 31400 53200 31800 4
+N 54700 33300 55700 33300 4
+N 55700 32800 55900 32800 4
+N 55700 33200 55900 33200 4
+N 55700 32400 55900 32400 4
+N 55700 32400 55700 33300 4
+N 52500 31800 55700 31800 4
+N 55700 31800 55700 32000 4
+N 55700 32000 55900 32000 4
+C 58200 33000 1 270 0 resistor-1.sym
+{
+T 58500 32600 5 10 1 1 180 8 1
+refdes=R201
+T 58200 33000 5 10 0 1 90 8 1
+footprint=0603
+T 58500 32400 5 10 1 1 0 0 1
+value=140K
+}
+C 58200 31900 1 270 0 resistor-1.sym
+{
+T 58500 31500 5 10 1 1 180 8 1
+refdes=R202
+T 58200 31900 5 10 0 1 90 8 1
+footprint=0603
+T 58500 31300 5 10 1 1 0 0 1
+value=78.7K
+}
+N 58300 30900 58300 31000 4
+N 57900 32000 58300 32000 4
+N 58300 31900 58300 32100 4
+N 58300 33000 58300 33700 4
+C 59200 33100 1 90 1 capacitor-1.sym
+{
+T 59100 32800 5 10 1 1 0 0 1
+refdes=C210
+T 59100 32400 5 10 1 1 0 0 1
+value=470pF
+T 59200 33100 5 10 0 1 0 6 1
+footprint=0603
+}
+N 58300 32000 59000 32000 4
+N 59000 32000 59000 32200 4
+N 59000 33200 59000 33100 4
+N 52500 33300 53800 33300 4
+C 53400 31400 1 180 0 generic-power.sym
+{
+T 53200 31150 5 10 1 1 180 3 1
+net=AGND:1
+}
+C 58500 30900 1 180 0 generic-power.sym
+{
+T 58300 30650 5 10 1 1 180 3 1
+net=AGND:1
+}
+C 52700 33600 1 0 1 generic-power.sym
+{
+T 52500 33850 5 10 1 1 180 5 1
+net=6V_RX:1
+}
+N 52500 33000 52500 33600 4
+C 43900 41500 1 0 0 generic-power.sym
+{
+T 44100 41750 5 10 1 1 0 3 1
+net=3_3V_SW:1
+}
+C 43900 36800 1 0 0 generic-power.sym
+{
+T 44100 37050 5 10 1 1 0 3 1
+net=3_3V_SW:1
+}
+C 42600 29500 1 0 0 7404-3.sym
+{
+T 44100 31500 5 10 1 1 0 0 1
+refdes=U204
+T 43000 29300 5 10 1 1 0 0 1
+net=3_3V_SW:14
+T 43000 29100 5 10 1 1 0 0 1
+net=AGND:7
+T 42600 29500 5 10 0 1 0 0 1
+footprint=SO14
+}
+N 44600 30600 46000 30600 4
+{
+T 45100 30600 5 10 1 1 0 0 1
+netname=TX
+}
+N 44600 30300 46000 30300 4
+{
+T 45100 30300 5 10 1 1 0 0 1
+netname=RX
+}
+N 44600 30000 46000 30000 4
+{
+T 45100 30000 5 10 1 1 0 0 1
+netname=RX1
+}
+N 44600 29700 46000 29700 4
+{
+T 45100 29700 5 10 1 1 0 0 1
+netname=RX2
+}
+N 43100 39500 44500 39500 4
+{
+T 43600 39500 5 10 1 1 0 0 1
+netname=TX
+}
+N 43100 39900 44500 39900 4
+{
+T 43600 39900 5 10 1 1 0 0 1
+netname=RX
+}
+N 43100 35200 44500 35200 4
+{
+T 43600 35200 5 10 1 1 0 0 1
+netname=RX1
+}
+N 43100 34800 44500 34800 4
+{
+T 43600 34800 5 10 1 1 0 0 1
+netname=RX2
+}
+N 41200 29700 42600 29700 4
+{
+T 41700 29700 5 10 1 1 0 0 1
+netname=RX1
+}
+N 41200 30300 42600 30300 4
+{
+T 41700 30300 5 10 1 1 0 0 1
+netname=TX
+}
+N 41200 30600 41200 30700 4
+C 41000 32100 1 0 0 generic-power.sym
+{
+T 41200 32350 5 10 1 1 0 3 1
+net=3_3V_SW:1
+}
+N 41200 31600 41200 32100 4
+C 41000 31600 1 90 1 resistor-1.sym
+{
+T 40700 31100 5 10 1 1 0 6 1
+value=10K
+T 41000 31600 5 10 0 1 270 2 1
+footprint=0603
+T 40700 30900 5 10 1 1 0 6 1
+refdes=R249
+}
+N 41200 31900 40900 31900 4
+N 40900 31900 40900 31600 4
+N 40900 30700 40900 30000 4
+N 40900 30000 42600 30000 4
+{
+T 41500 30000 5 10 1 1 0 0 1
+netname=io_rx_06
+}
+N 41200 31900 42200 31900 4
+N 42200 31900 42200 30900 4
+N 42200 30900 42600 30900 4
+N 42200 31200 42600 31200 4
+T 53700 34400 9 25 1 0 0 0 1
+Always On
+C 49400 39900 1 90 0 capacitor-1.sym
+{
+T 49300 40500 5 10 1 1 0 0 1
+refdes=C221
+T 49300 40100 5 10 1 1 0 0 1
+value=3.9pF
+T 49400 39900 5 10 0 1 0 8 1
+footprint=0603
+}
+C 49000 39900 1 90 0 inductor-1.sym
+{
+T 48400 40500 5 10 1 1 0 0 1
+refdes=L221
+T 49000 39900 5 10 0 1 90 0 1
+footprint=0603
+T 48800 40200 5 10 1 1 0 6 1
+value=NONE
+}
+N 48900 39900 48900 39800 4
+N 48900 39800 49200 39800 4
+N 48900 40800 48900 40900 4
+N 48900 40900 49200 40900 4
+N 49200 40900 49200 40800 4
+C 51000 39900 1 90 0 capacitor-1.sym
+{
+T 50900 40500 5 10 1 1 0 0 1
+refdes=C222
+T 50900 40100 5 10 1 1 0 0 1
+value=12pF
+T 51000 39900 5 10 0 1 0 8 1
+footprint=0603
+}
+C 50600 39900 1 90 0 inductor-1.sym
+{
+T 49900 40500 5 10 1 1 0 0 1
+refdes=L222
+T 50600 39900 5 10 0 1 90 0 1
+footprint=0603
+T 50400 40200 5 10 1 1 0 6 1
+value=NONE
+}
+N 50500 39900 50500 39800 4
+N 50500 39800 50800 39800 4
+N 50800 39800 50800 39900 4
+N 50500 40800 50500 40900 4
+N 50500 40900 50800 40900 4
+N 50800 40900 50800 40800 4
+C 52600 39900 1 90 0 capacitor-1.sym
+{
+T 52500 40500 5 10 1 1 0 0 1
+refdes=C223
+T 52500 40100 5 10 1 1 0 0 1
+value=3.9pF
+T 52600 39900 5 10 0 1 0 8 1
+footprint=0603
+}
+C 52200 39900 1 90 0 inductor-1.sym
+{
+T 51500 40500 5 10 1 1 0 0 1
+refdes=L223
+T 52200 39900 5 10 0 1 90 0 1
+footprint=0603
+T 52000 40200 5 10 1 1 0 6 1
+value=NONE
+}
+N 52100 39800 52400 39800 4
+N 52400 39800 52400 39900 4
+N 52100 40800 52100 40900 4
+N 52100 40900 52400 40900 4
+N 52400 40900 52400 40800 4
+C 49400 40800 1 0 0 capacitor-1.sym
+{
+T 49900 41100 5 10 1 1 0 0 1
+refdes=C224
+T 49400 41100 5 10 1 1 0 0 1
+value=NONE
+T 49400 40800 5 10 0 1 270 8 1
+footprint=0603
+}
+C 49400 41200 1 0 0 inductor-1.sym
+{
+T 49900 41400 5 10 1 1 0 0 1
+refdes=L224
+T 49400 41200 5 10 0 1 0 0 1
+footprint=0603
+T 49400 41400 5 10 1 1 0 0 1
+value=22nH
+}
+N 49400 41300 49300 41300 4
+N 49300 41300 49300 41000 4
+N 49300 41000 49400 41000 4
+N 50300 41300 50400 41300 4
+N 50400 41300 50400 41000 4
+N 50400 41000 50300 41000 4
+C 51000 40800 1 0 0 capacitor-1.sym
+{
+T 51500 41100 5 10 1 1 0 0 1
+refdes=C225
+T 51000 41100 5 10 1 1 0 0 1
+value=NONE
+T 51000 40800 5 10 0 1 270 8 1
+footprint=0603
+}
+C 51000 41200 1 0 0 inductor-1.sym
+{
+T 51500 41400 5 10 1 1 0 0 1
+refdes=L225
+T 51000 41200 5 10 0 1 0 0 1
+footprint=0603
+T 51000 41400 5 10 1 1 0 0 1
+value=22nH
+}
+N 51000 41300 50900 41300 4
+N 50900 41300 50900 41000 4
+N 50900 41000 51000 41000 4
+N 51900 41300 52000 41300 4
+N 52000 41300 52000 41000 4
+N 52000 41000 51900 41000 4
+N 47800 41100 49300 41100 4
+N 50400 41100 50900 41100 4
+N 52000 41100 53400 41100 4
+N 52300 41100 52300 40900 4
+N 50700 41100 50700 40900 4
+N 49100 41100 49100 40900 4
+C 50700 39300 1 180 0 generic-power.sym
+{
+T 50500 39050 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 49200 39500 49200 39900 4
+N 49200 39500 52100 39500 4
+N 52100 39500 52100 39900 4
+N 50700 39800 50700 39500 4
+N 50500 39500 50500 39300 4
+C 60300 33100 1 90 1 capacitor-1.sym
+{
+T 60200 32800 5 10 1 1 0 0 1
+refdes=C240
+T 60200 32400 5 10 1 1 0 0 1
+value=1uF
+T 60300 33100 5 10 0 1 0 6 1
+footprint=0603
+}
+N 58300 33200 60100 33200 4
+N 60100 33200 60100 33100 4
+N 60100 32100 60100 32200 4
+C 60300 32100 1 180 0 generic-power.sym
+{
+T 60100 31850 5 10 1 1 180 3 1
+net=AGND:1
+}
diff --git a/usrp-hw/rfx/common900.sch b/usrp-hw/rfx/common900.sch
new file mode 100644
index 000000000..92a964844
--- /dev/null
+++ b/usrp-hw/rfx/common900.sch
@@ -0,0 +1,535 @@
+v 20050820 1
+C 39500 25900 0 0 0 title-C.sym
+C 52000 40600 1 0 1 BNC-1.sym
+{
+T 52000 41400 5 10 1 1 0 6 1
+refdes=J200
+T 52000 40600 5 10 0 1 0 0 1
+footprint=SMA_VERT
+}
+C 52100 40300 1 180 0 generic-power.sym
+{
+T 51900 40050 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 51900 40600 51900 40300 4
+C 44000 40500 1 180 0 capacitor-1.sym
+{
+T 43700 40400 5 10 1 1 0 0 1
+refdes=C201
+T 44400 40100 5 10 1 1 0 6 1
+value=220pF
+T 44000 40500 5 10 0 1 270 0 1
+footprint=0603
+}
+C 42500 40900 1 180 1 capacitor-1.sym
+{
+T 42900 40800 5 10 1 1 180 2 1
+refdes=C202
+T 42900 40500 5 10 1 1 180 2 1
+value=220pF
+T 42500 40900 5 10 0 1 270 2 1
+footprint=0603
+}
+C 43800 38400 1 180 1 generic-power.sym
+{
+T 44000 38150 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 44000 40300 44500 40300 4
+N 44500 40700 43400 40700 4
+N 43100 40300 42000 40300 4
+{
+T 42100 40300 5 10 1 1 0 0 1
+netname=RF_TX
+}
+N 41200 30600 44800 30600 4
+{
+T 41500 30600 5 10 1 1 0 0 1
+netname=io_tx_06
+}
+T 40300 26300 9 15 1 0 0 0 6
+Band
+400 - 500 MHz
+800 - 975 MHz
+1.2 - 1.3 GHz
+2.3 - 2.4 GHz
+2.4 - 2.7 GHz
+T 47100 26300 9 15 1 0 0 0 6
+Upconverter VCO
+ADF4360-7 (Div by 2)
+ADF4360-3 (Div by 2)
+ADF4360-0 (Div by 2)
+ADF4360-1
+ADF4360-0
+T 42900 26300 9 15 1 0 0 0 6
+Upconverter
+AD8345
+AD8349
+AD8349
+AD8349
+AD8349
+T 44900 26300 9 15 1 0 0 0 6
+Downconverter
+AD8348
+AD8347
+AD8347
+AD8347
+AD8347
+T 50300 26300 9 15 1 0 0 0 6
+Downconverter VCO
+ADF4360-3 (Div by 2)
+Same
+Same
+Same
+Same
+T 56600 26600 5 10 1 1 0 0 1
+date=$Date: 2006/03/10 05:27:22 $
+T 58500 26300 5 10 1 1 0 0 1
+rev=$Revision: 1.2 $
+T 58600 26000 5 10 1 1 0 0 1
+auth=$Author: matt $
+T 54400 26300 5 10 1 1 0 0 1
+fname=$Source: /opt/usrp-hw-cvs/usrp-hw/flex_xcvr/common900.sch,v $
+T 57800 27000 8 14 1 1 0 4 1
+title=Flex900 Common
+T 55400 26000 9 10 1 0 0 0 1
+1
+T 56200 26000 9 10 1 0 0 0 1
+3
+C 44400 38200 1 0 0 hmc174ms8.sym
+{
+T 45700 41800 5 10 1 1 0 6 1
+refdes=U202
+}
+C 48800 40900 1 0 0 capacitor-1.sym
+{
+T 49200 41000 5 10 1 1 180 0 1
+refdes=C204
+T 50100 41000 5 10 1 1 180 0 1
+value=NONE
+T 48800 40900 5 10 0 1 270 8 1
+footprint=0603
+}
+N 46500 41100 48800 41100 4
+N 44100 41500 44100 41100 4
+N 44100 41100 44500 41100 4
+N 44000 38400 44000 39100 4
+N 44000 39100 44500 39100 4
+N 44500 38700 44000 38700 4
+T 46400 38600 9 10 1 0 0 0 2
+B high selects  RF1
+A high selects RF2
+C 40800 35100 1 0 0 BNC-1.sym
+{
+T 40800 35900 5 10 1 1 0 0 1
+refdes=J202
+T 40800 35100 5 10 0 1 0 6 1
+footprint=SMA_VERT
+}
+C 40700 34800 1 180 1 generic-power.sym
+{
+T 40900 34550 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 40900 35100 40900 34800 4
+C 43400 35800 1 180 1 capacitor-1.sym
+{
+T 43800 35700 5 10 1 1 180 2 1
+refdes=C206
+T 43800 35400 5 10 1 1 180 2 1
+value=220pF
+T 43400 35800 5 10 0 1 270 2 1
+footprint=0603
+}
+C 43800 33700 1 180 1 generic-power.sym
+{
+T 44000 33450 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 44500 36000 41800 36000 4
+C 44400 33500 1 0 0 hmc174ms8.sym
+{
+T 45700 37100 5 10 1 1 0 6 1
+refdes=U209
+}
+C 46900 36200 1 0 0 capacitor-1.sym
+{
+T 47300 36300 5 10 1 1 180 0 1
+refdes=C205
+T 48200 36300 5 10 1 1 180 0 1
+value=220pF
+T 46900 36200 5 10 0 1 270 8 1
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+}
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+TX/RX
+T 40400 35400 9 30 1 0 0 6 1
+RX
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+}
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+A1	B1	A2	B2
+0	0	0	0		All Off
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+0	1	0	0		TX Only
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+0	1	0	1		Full Duplex TX and RX
+
+0	0	0	1		RX from secondary RX port
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+1	0	1	0		RX from primary TX/RX port
+
+0	0	1	0		Nothing
+1	0	0	0		Nothing
+
+0	0	1	1		BAD!
+0	1	1	1		BAD!
+1	0	1	1		BAD!
+1	1	0	0		BAD!
+1	1	0	1		BAD!
+1	1	1	0		BAD!
+1	1	1	1		BAD!
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+{
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+value=10K
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+{
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+}
diff --git a/usrp-hw/rfx/rcv.sch b/usrp-hw/rfx/rcv.sch
new file mode 100644
index 000000000..79273ff1b
--- /dev/null
+++ b/usrp-hw/rfx/rcv.sch
@@ -0,0 +1,2099 @@
+v 20050820 1
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+{
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
+N 95500 35100 95500 35500 4
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+T 68500 49400 9 10 1 0 0 0 6
+Max Gain
+22
+45.5
+-6
+20
+81.5
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+Min Gain
+22
+1.5
+-6
+0
+17.5
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+LNA
+AD8348
+Filter
+AD9862 ADC
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+T 66900 49000 9 10 1 0 0 0 1
+At max gain, thermal noise will be approx 5% of max scale
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+}
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+}
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diff --git a/usrp-hw/rfx/rcv2400.sch b/usrp-hw/rfx/rcv2400.sch
new file mode 100644
index 000000000..f6eda06a3
--- /dev/null
+++ b/usrp-hw/rfx/rcv2400.sch
@@ -0,0 +1,2089 @@
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+T 96100 39800 5 10 0 1 180 0 1
+footprint=0603
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+refdes=R32
+}
+N 94800 39700 95200 39700 4
+N 96100 39700 96500 39700 4
+N 94800 39100 95200 39100 4
+N 93900 40300 93700 40300 4
+N 93700 39100 93900 39100 4
+N 93700 39700 93900 39700 4
+N 95000 39100 95000 38700 4
+N 95000 38700 91100 38700 4
+N 91100 38700 91100 40800 4
+N 91100 40800 91400 40800 4
+C 90100 41400 1 180 1 capacitor-1.sym
+{
+T 90400 41300 5 10 1 1 0 6 1
+refdes=C70
+T 91000 41300 5 10 1 1 0 6 1
+value=1000pF
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+footprint=0603
+}
+N 91400 41200 91000 41200 4
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+{
+T 89900 40750 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 89900 41200 90100 41200 4
+C 91000 41700 1 180 0 resistor-1.sym
+{
+T 90900 41700 5 10 1 1 0 0 1
+value=4.7K
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+footprint=0603
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+}
+N 91000 41600 91400 41600 4
+N 90100 41600 89900 41600 4
+N 89900 41000 89900 41600 4
+C 90100 42200 1 180 1 capacitor-1.sym
+{
+T 90400 42100 5 10 1 1 0 6 1
+refdes=C71
+T 91100 42100 5 10 1 1 0 6 1
+value=10uF
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+}
+N 91000 42000 91400 42000 4
+N 89900 42000 90100 42000 4
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+{
+T 86800 42300 5 10 1 1 0 0 1
+value=NONE
+T 87000 42300 5 10 0 1 180 0 1
+footprint=0603
+T 86100 42300 5 10 1 1 0 0 1
+refdes=R34
+}
+C 87000 42700 1 180 0 resistor-1.sym
+{
+T 86900 42700 5 10 1 1 0 0 1
+value=0
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+}
+N 90800 42400 91400 42400 4
+N 87800 42600 87000 42600 4
+N 86100 42200 84900 42200 4
+{
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+netname=io_rx_00
+}
+C 87800 42800 1 180 1 capacitor-1.sym
+{
+T 88100 42700 5 10 1 1 0 6 1
+refdes=C81
+T 88800 42700 5 10 1 1 0 6 1
+value=.01uF
+T 87800 42800 5 10 0 1 270 2 1
+footprint=0603
+}
+C 88800 42300 1 270 0 resistor-1.sym
+{
+T 89300 42200 5 10 1 1 180 0 1
+value=50
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+footprint=0603
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+refdes=R37
+}
+C 89100 42800 1 180 1 capacitor-1.sym
+{
+T 89400 42700 5 10 1 1 0 6 1
+refdes=C80
+T 90100 42700 5 10 1 1 0 6 1
+value=.01uF
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+footprint=0603
+}
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+N 88900 41200 89900 41200 4
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+N 90800 42600 90000 42600 4
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+N 88900 42300 88900 42600 4
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+N 93800 43600 94600 43600 4
+N 94600 43600 94600 43400 4
+N 97600 47900 99300 47900 4
+{
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+netname=VINP_A
+}
+N 97600 47500 99300 47500 4
+{
+T 98200 47500 5 10 1 1 0 0 1
+netname=VINN_A
+}
+N 97600 46700 99300 46700 4
+{
+T 98200 46700 5 10 1 1 0 0 1
+netname=VINN_B
+}
+N 97600 47100 99300 47100 4
+{
+T 98200 47100 5 10 1 1 0 0 1
+netname=VINP_B
+}
+C 86900 49200 1 180 0 resistor-1.sym
+{
+T 86500 49300 5 10 1 1 0 0 1
+value=95.3
+T 86900 49200 5 10 0 1 180 0 1
+footprint=0603
+T 86100 49300 5 10 1 1 0 0 1
+refdes=R61
+}
+C 87400 49000 1 0 0 inductor-1.sym
+{
+T 87500 49300 5 10 1 1 0 0 1
+refdes=L1
+T 87400 49000 5 10 0 1 0 0 1
+footprint=1008
+T 87900 49300 5 10 1 1 0 0 1
+value=0.68uH
+}
+C 89600 49200 1 180 0 resistor-1.sym
+{
+T 89400 49300 5 10 1 1 0 0 1
+value=2
+T 89600 49200 5 10 0 1 180 0 1
+footprint=0603
+T 89000 49300 5 10 1 1 0 0 1
+refdes=R3
+}
+C 90100 49000 1 0 0 inductor-1.sym
+{
+T 90200 49300 5 10 1 1 0 0 1
+refdes=L3
+T 90100 49000 5 10 0 1 0 0 1
+footprint=1008
+T 90600 49300 5 10 1 1 0 0 1
+value=1.2uH
+}
+C 92300 49200 1 180 0 resistor-1.sym
+{
+T 92200 49200 5 10 1 1 0 0 1
+value=2
+T 92300 49200 5 10 0 1 180 0 1
+footprint=0603
+T 91600 49300 5 10 1 1 0 0 1
+refdes=R5
+}
+C 88000 50100 1 180 1 capacitor-1.sym
+{
+T 88300 50000 5 10 1 1 0 6 1
+refdes=C92
+T 89000 50100 5 10 1 1 0 6 1
+value=4.7pF
+T 88000 50100 5 10 0 1 270 2 1
+footprint=0603
+}
+C 90700 50100 1 180 1 capacitor-1.sym
+{
+T 91000 50000 5 10 1 1 0 6 1
+refdes=C91
+T 91700 50100 5 10 1 1 0 6 1
+value=8.2pF
+T 90700 50100 5 10 0 1 270 2 1
+footprint=0603
+}
+C 90100 48900 1 90 1 capacitor-1.sym
+{
+T 90000 48600 5 10 1 1 0 0 1
+refdes=C90
+T 90000 48200 5 10 1 1 0 0 1
+value=150pF
+T 90100 48900 5 10 0 1 180 2 1
+footprint=0603
+}
+C 92900 48900 1 90 1 capacitor-1.sym
+{
+T 92800 48600 5 10 1 1 0 0 1
+refdes=C89
+T 92800 48200 5 10 1 1 0 0 1
+value=82pF
+T 92900 48900 5 10 0 1 180 2 1
+footprint=0603
+}
+C 93600 48000 1 90 0 resistor-1.sym
+{
+T 93700 48200 5 10 1 1 0 0 1
+value=100
+T 93600 48000 5 10 0 1 90 0 1
+footprint=0603
+T 93700 48500 5 10 1 1 0 0 1
+refdes=R7
+}
+N 86900 49100 87400 49100 4
+N 88300 49100 88700 49100 4
+N 89600 49100 90100 49100 4
+N 89900 49100 89900 48900 4
+N 91000 49100 91400 49100 4
+N 93500 49100 93500 48900 4
+N 92700 49100 92700 48900 4
+N 87200 49100 87200 49900 4
+N 87200 49900 88000 49900 4
+N 89900 49900 89900 49100 4
+N 88900 49900 90700 49900 4
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+N 89900 47800 89900 48000 4
+N 88200 47800 93500 47800 4
+{
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+netname=vref_rx
+}
+C 86900 46600 1 180 0 resistor-1.sym
+{
+T 86500 46700 5 10 1 1 0 0 1
+value=95.3
+T 86900 46600 5 10 0 1 180 0 1
+footprint=0603
+T 86100 46700 5 10 1 1 0 0 1
+refdes=R87
+}
+C 87400 46400 1 0 0 inductor-1.sym
+{
+T 87500 46700 5 10 1 1 0 0 1
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+T 87400 46400 5 10 0 1 0 0 1
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+T 87900 46700 5 10 1 1 0 0 1
+value=0.68uH
+}
+C 89600 46600 1 180 0 resistor-1.sym
+{
+T 89400 46700 5 10 1 1 0 0 1
+value=2
+T 89600 46600 5 10 0 1 180 0 1
+footprint=0603
+T 88900 46700 5 10 1 1 0 0 1
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+}
+C 90100 46400 1 0 0 inductor-1.sym
+{
+T 90200 46700 5 10 1 1 0 0 1
+refdes=L4
+T 90100 46400 5 10 0 1 0 0 1
+footprint=1008
+T 90600 46700 5 10 1 1 0 0 1
+value=1.2uH
+}
+C 92300 46600 1 180 0 resistor-1.sym
+{
+T 92200 46600 5 10 1 1 0 0 1
+value=2
+T 92300 46600 5 10 0 1 180 0 1
+footprint=0603
+T 91500 46700 5 10 1 1 0 0 1
+refdes=R6
+}
+C 88000 47500 1 180 1 capacitor-1.sym
+{
+T 88300 47400 5 10 1 1 0 6 1
+refdes=C88
+T 89000 47500 5 10 1 1 0 6 1
+value=4.7pF
+T 88000 47500 5 10 0 1 270 2 1
+footprint=0603
+}
+C 90700 47500 1 180 1 capacitor-1.sym
+{
+T 90700 47400 5 10 1 1 0 0 1
+refdes=C87
+T 91300 47400 5 10 1 1 0 0 1
+value=8.2pF
+T 90700 47500 5 10 0 1 270 2 1
+footprint=0603
+}
+C 90100 46300 1 90 1 capacitor-1.sym
+{
+T 90000 46000 5 10 1 1 0 0 1
+refdes=C86
+T 90500 45500 5 10 1 1 0 6 1
+value=150pF
+T 90100 46300 5 10 0 1 180 2 1
+footprint=0603
+}
+C 92900 46300 1 90 1 capacitor-1.sym
+{
+T 92800 46000 5 10 1 1 0 0 1
+refdes=C85
+T 93300 45500 5 10 1 1 0 6 1
+value=82pF
+T 92900 46300 5 10 0 1 180 2 1
+footprint=0603
+}
+C 93600 45400 1 90 0 resistor-1.sym
+{
+T 93700 45700 5 10 1 1 0 0 1
+value=100
+T 93600 45400 5 10 0 1 90 0 1
+footprint=0603
+T 93700 46000 5 10 1 1 0 0 1
+refdes=R8
+}
+N 86900 46500 87400 46500 4
+N 88300 46500 88700 46500 4
+N 89600 46500 90100 46500 4
+N 89900 46500 89900 46300 4
+N 91000 46500 91400 46500 4
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+N 87200 46500 87200 47300 4
+N 87200 47300 88000 47300 4
+N 89900 47300 89900 46500 4
+N 88900 47300 90700 47300 4
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+N 93500 45400 93500 45200 4
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+N 89900 45200 89900 45400 4
+N 88200 45200 93500 45200 4
+{
+T 88400 45200 5 10 1 1 0 0 1
+netname=vref_rx
+}
+N 92300 46500 94100 46500 4
+N 84400 47500 94300 47500 4
+N 92300 49100 94100 49100 4
+N 94100 47900 94300 47900 4
+N 83600 48200 85400 48200 4
+N 85400 48200 85400 49100 4
+N 85400 49100 86000 49100 4
+N 86000 46500 85400 46500 4
+N 85400 46500 85400 47800 4
+N 85400 47800 83600 47800 4
+N 94100 47900 94100 49100 4
+N 94100 46500 94100 47500 4
+N 77300 33600 79300 33600 4
+C 73800 34000 1 0 0 generic-power.sym
+{
+T 74000 34250 5 10 1 1 180 5 1
+net=5V_RX:1
+}
+C 73900 32000 1 270 0 resistor-1.sym
+{
+T 73700 31800 5 10 1 1 270 0 1
+value=1K
+T 73900 32000 5 10 0 1 270 0 1
+footprint=0603
+T 74200 31700 5 10 1 1 270 0 1
+refdes=R11
+}
+C 73900 33400 1 270 0 resistor-1.sym
+{
+T 73700 33200 5 10 1 1 270 0 1
+value=2K
+T 73900 33400 5 10 0 1 270 0 1
+footprint=0603
+T 74200 33100 5 10 1 1 270 0 1
+refdes=R10
+}
+C 77500 31600 1 90 1 capacitor-1.sym
+{
+T 77400 31300 5 10 1 1 0 0 1
+refdes=C84
+T 77700 30800 5 10 1 1 0 6 1
+value=0.1uF
+T 77500 31600 5 10 0 1 180 2 1
+footprint=0603
+}
+N 74000 30500 74000 31100 4
+N 74000 32000 74000 32500 4
+N 74000 33400 74000 34000 4
+C 78000 31600 1 90 1 capacitor-1.sym
+{
+T 77900 31300 5 10 1 1 0 0 1
+refdes=C83
+T 78200 30800 5 10 1 1 0 6 1
+value=0.1uF
+T 78000 31600 5 10 0 1 180 2 1
+footprint=0603
+}
+C 78500 31600 1 90 1 capacitor-1.sym
+{
+T 78400 31300 5 10 1 1 0 0 1
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+T 78700 30800 5 10 1 1 0 6 1
+value=0.1uF
+T 78500 31600 5 10 0 1 180 2 1
+footprint=0603
+}
+N 78300 31600 78300 32800 4
+N 78300 32800 79300 32800 4
+N 77800 31600 77800 33200 4
+N 77800 33200 79300 33200 4
+N 77300 31600 77300 34700 4
+C 78000 30300 1 180 0 generic-power.sym
+{
+T 77800 30050 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 77300 30700 77300 30500 4
+N 77800 30300 77800 30700 4
+N 77800 30500 78300 30500 4
+N 78300 30500 78300 30700 4
+N 80700 48600 81600 48600 4
+{
+T 80900 48600 5 10 1 1 0 0 1
+netname=LON
+}
+N 77400 47000 79400 47000 4
+{
+T 77600 47000 5 10 1 1 0 0 1
+netname=AUX_DAC_A_RX
+}
+C 79400 47100 1 180 1 resistor-1.sym
+{
+T 80100 47100 5 10 1 1 0 0 1
+value=0
+T 79400 47100 5 10 0 1 0 2 1
+footprint=0603
+T 79500 47100 5 10 1 1 0 0 1
+refdes=R95
+}
+C 79400 46700 1 180 1 resistor-1.sym
+{
+T 79800 46800 5 10 1 1 0 6 1
+value=NONE
+T 79400 46700 5 10 0 1 0 2 1
+footprint=0603
+T 80300 46400 5 10 1 1 0 6 1
+refdes=R96
+}
+N 78500 46600 79400 46600 4
+C 79200 46400 1 90 1 capacitor-1.sym
+{
+T 79100 46100 5 10 1 1 0 0 1
+refdes=C95
+T 79400 45600 5 10 1 1 0 6 1
+value=0.1uF
+T 79200 46400 5 10 0 1 180 2 1
+footprint=0603
+}
+C 78800 45400 1 180 1 generic-power.sym
+{
+T 79000 45150 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 79000 45400 79000 45500 4
+C 77600 46700 1 180 1 resistor-1.sym
+{
+T 77900 46900 5 10 1 1 180 6 1
+value=NONE
+T 77600 46700 5 10 0 1 0 2 1
+footprint=0603
+T 77800 46400 5 10 1 1 180 6 1
+refdes=R97
+}
+N 79000 46400 79000 46600 4
+N 76300 46600 77600 46600 4
+{
+T 76500 46600 5 10 1 1 0 0 1
+netname=io_rx_08
+}
+N 68200 42600 67900 42600 4
+C 80100 48000 1 180 1 capacitor-1.sym
+{
+T 80400 47900 5 10 1 1 0 6 1
+refdes=C94
+T 81300 47900 5 10 1 1 0 6 1
+value=100pF
+T 80100 48000 5 10 0 1 270 2 1
+footprint=0603
+}
+C 80300 47600 1 180 1 capacitor-1.sym
+{
+T 80500 47500 5 10 1 1 0 6 1
+refdes=C93
+T 81500 47500 5 10 1 1 0 6 1
+value=100pF
+T 80300 47600 5 10 0 1 270 2 1
+footprint=0603
+}
+N 81000 47800 81600 47800 4
+N 81600 47400 81200 47400 4
+C 79500 47600 1 270 1 resistor-1.sym
+{
+T 79400 48000 5 10 1 1 0 6 1
+value=200
+T 79500 47600 5 10 0 1 90 2 1
+footprint=0603
+T 79100 48200 5 10 1 1 0 0 1
+refdes=R18
+}
+C 79200 47600 1 90 1 generic-power.sym
+{
+T 78950 47400 5 10 1 1 90 3 1
+net=AGND:1
+}
+N 79200 47400 80300 47400 4
+N 80100 47800 79900 47800 4
+N 79600 48700 79600 48500 4
+N 79600 47600 79600 47400 4
+C 94300 35500 1 0 0 generic-power.sym
+{
+T 94500 35750 5 10 1 1 180 5 1
+net=5V_RX:1
+}
+N 94500 35100 94500 35500 4
+T 68500 49400 9 10 1 0 0 0 6
+Max Gain
+22
+45.5
+-6
+20
+81.5
+T 70000 49400 9 10 1 0 0 0 6
+Min Gain
+22
+1.5
+-6
+0
+17.5
+T 66900 49400 9 10 1 0 0 0 6
+Stage
+LNA
+AD8348
+Filter
+AD9862 ADC
+Sum
+T 66900 49000 9 10 1 0 0 0 1
+At max gain, thermal noise will be approx 5% of max scale
+C 77400 48900 1 180 1 capacitor-1.sym
+{
+T 78000 48800 5 10 1 1 0 0 1
+refdes=C96
+T 78000 48600 5 10 1 1 180 6 1
+value=100pF
+T 77400 48900 5 10 0 1 270 2 1
+footprint=0603
+}
+C 77100 49900 1 270 0 inductor-1.sym
+{
+T 77400 49600 5 10 1 1 0 0 1
+refdes=L98
+T 77100 49900 5 10 0 1 270 0 1
+footprint=0603
+T 77400 49400 5 10 1 1 0 0 1
+value=23nH
+}
+N 76900 48700 77400 48700 4
+N 77200 48700 77200 49000 4
+C 77900 50900 1 180 1 capacitor-1.sym
+{
+T 78500 50800 5 10 1 1 0 0 1
+refdes=C98
+T 78500 50600 5 10 1 1 180 6 1
+value=0.1uF
+T 77900 50900 5 10 0 1 270 2 1
+footprint=0603
+}
+C 77900 50300 1 180 1 capacitor-1.sym
+{
+T 78500 50200 5 10 1 1 0 0 1
+refdes=C97
+T 78500 50000 5 10 1 1 180 6 1
+value=100pF
+T 77900 50300 5 10 0 1 270 2 1
+footprint=0603
+}
+N 76900 50100 77900 50100 4
+N 77700 50100 77700 50700 4
+N 77700 50700 77900 50700 4
+C 79600 50200 1 270 1 generic-power.sym
+{
+T 79850 50400 5 10 1 1 270 3 1
+net=AGND:1
+}
+N 79600 50400 79300 50400 4
+N 79300 50700 78800 50700 4
+N 78800 50100 79300 50100 4
+N 79300 50100 79300 50700 4
+N 96500 38600 96500 41600 4
+C 80700 46500 1 90 1 capacitor-1.sym
+{
+T 80600 46200 5 10 1 1 0 0 1
+refdes=C33
+T 80900 45700 5 10 1 1 0 6 1
+value=0.1uF
+T 80700 46500 5 10 0 1 180 2 1
+footprint=0603
+}
+C 80300 45500 1 180 1 generic-power.sym
+{
+T 80500 45250 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 80500 45500 80500 45600 4
+N 80300 46600 80500 46600 4
+N 80300 47000 81600 47000 4
+N 80500 46500 80500 47000 4
+C 71400 44500 1 0 0 header16-1.sym
+{
+T 71900 47800 5 10 1 1 0 0 1
+refdes=J24
+T 71400 44500 5 10 0 1 0 0 1
+footprint=CONNECTOR16
+}
+N 72800 46300 73100 46300 4
+N 72800 47500 73000 47500 4
+N 73000 47500 73000 46300 4
+N 73000 46300 73000 44700 4
+N 73000 44700 72800 44700 4
+N 72800 47100 73000 47100 4
+N 72800 46700 73000 46700 4
+N 72800 45900 73000 45900 4
+N 72800 45500 73000 45500 4
+N 72800 45100 73000 45100 4
+N 69800 46700 71400 46700 4
+{
+T 70200 46700 5 10 1 1 0 0 1
+netname=io_rx_13
+}
+N 69800 47500 71400 47500 4
+{
+T 70200 47500 5 10 1 1 0 0 1
+netname=io_rx_15
+}
+N 69800 45900 71400 45900 4
+{
+T 70200 45900 5 10 1 1 0 0 1
+netname=io_rx_11
+}
+N 69800 45100 71400 45100 4
+{
+T 70200 45100 5 10 1 1 0 0 1
+netname=io_rx_09
+}
+N 69800 47100 71400 47100 4
+{
+T 70200 47100 5 10 1 1 0 0 1
+netname=io_rx_14
+}
+N 69800 45500 71400 45500 4
+{
+T 70200 45500 5 10 1 1 0 0 1
+netname=io_rx_10
+}
+N 69800 46300 71400 46300 4
+{
+T 70200 46300 5 10 1 1 0 0 1
+netname=io_rx_12
+}
+N 69800 44700 71400 44700 4
+{
+T 70200 44700 5 10 1 1 0 0 1
+netname=io_rx_08
+}
+T 66200 44500 9 15 1 0 0 0 10
+RX Nets
+refclk_rx
+SDO_RX
+lockdet_rx
+SCLK_RX
+SEN_RX
+RX Enable
+RX1 / RX2
+RX Power
+digital agc
+T 68300 44500 9 15 1 0 0 0 10
+Pin
+io_rx_00
+io_rx_01
+io_rx_02
+io_rx_03
+io_rx_04
+io_rx_05
+io_rx_06
+io_rx_07
+io_rx_08
+N 70800 36200 72200 36200 4
+{
+T 71200 36200 5 10 1 1 0 0 1
+netname=SEN_RX
+}
+N 70800 37400 72200 37400 4
+{
+T 71200 37400 5 10 1 1 0 0 1
+netname=SCLK_RX
+}
+N 70800 36600 72200 36600 4
+{
+T 71200 36600 5 10 1 1 0 0 1
+netname=SDO_RX
+}
+C 70800 37500 1 180 0 resistor-1.sym
+{
+T 70700 37500 5 10 1 1 0 0 1
+value=0
+T 70800 37500 5 10 0 1 180 0 1
+footprint=0603
+T 69900 37500 5 10 1 1 0 0 1
+refdes=R40
+}
+N 69900 37400 69600 37400 4
+C 73100 37500 1 180 0 resistor-1.sym
+{
+T 73000 37500 5 10 1 1 0 0 1
+value=None
+T 73100 37500 5 10 0 1 180 0 1
+footprint=0603
+T 72200 37500 5 10 1 1 0 0 1
+refdes=R43
+}
+C 73100 36700 1 180 0 resistor-1.sym
+{
+T 73000 36700 5 10 1 1 0 0 1
+value=None
+T 73100 36700 5 10 0 1 180 0 1
+footprint=0603
+T 72200 36700 5 10 1 1 0 0 1
+refdes=R44
+}
+N 74500 37400 73100 37400 4
+{
+T 74400 37400 5 10 1 1 0 6 1
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+}
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diff --git a/usrp-hw/rfx/rcv400.sch b/usrp-hw/rfx/rcv400.sch
new file mode 100644
index 000000000..302392221
--- /dev/null
+++ b/usrp-hw/rfx/rcv400.sch
@@ -0,0 +1,2103 @@
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+T 87900 49300 5 10 1 1 0 0 1
+value=0.68uH
+}
+C 89600 49200 1 180 0 resistor-1.sym
+{
+T 89400 49300 5 10 1 1 0 0 1
+value=2
+T 89600 49200 5 10 0 1 180 0 1
+footprint=0603
+T 89000 49300 5 10 1 1 0 0 1
+refdes=R3
+}
+C 90100 49000 1 0 0 inductor-1.sym
+{
+T 90200 49300 5 10 1 1 0 0 1
+refdes=L3
+T 90100 49000 5 10 0 1 0 0 1
+footprint=1008
+T 90600 49300 5 10 1 1 0 0 1
+value=1.2uH
+}
+C 92300 49200 1 180 0 resistor-1.sym
+{
+T 92200 49200 5 10 1 1 0 0 1
+value=2
+T 92300 49200 5 10 0 1 180 0 1
+footprint=0603
+T 91600 49300 5 10 1 1 0 0 1
+refdes=R5
+}
+C 88000 50100 1 180 1 capacitor-1.sym
+{
+T 88300 50000 5 10 1 1 0 6 1
+refdes=C92
+T 89000 50100 5 10 1 1 0 6 1
+value=4.7pF
+T 88000 50100 5 10 0 1 270 2 1
+footprint=0603
+}
+C 90700 50100 1 180 1 capacitor-1.sym
+{
+T 91000 50000 5 10 1 1 0 6 1
+refdes=C91
+T 91700 50100 5 10 1 1 0 6 1
+value=8.2pF
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+footprint=0603
+}
+C 90100 48900 1 90 1 capacitor-1.sym
+{
+T 90000 48600 5 10 1 1 0 0 1
+refdes=C90
+T 90000 48200 5 10 1 1 0 0 1
+value=150pF
+T 90100 48900 5 10 0 1 180 2 1
+footprint=0603
+}
+C 92900 48900 1 90 1 capacitor-1.sym
+{
+T 92800 48600 5 10 1 1 0 0 1
+refdes=C89
+T 92800 48200 5 10 1 1 0 0 1
+value=82pF
+T 92900 48900 5 10 0 1 180 2 1
+footprint=0603
+}
+C 93600 48000 1 90 0 resistor-1.sym
+{
+T 93700 48200 5 10 1 1 0 0 1
+value=100
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+footprint=0603
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+refdes=R7
+}
+N 86900 49100 87400 49100 4
+N 88300 49100 88700 49100 4
+N 89600 49100 90100 49100 4
+N 89900 49100 89900 48900 4
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+N 93500 49100 93500 48900 4
+N 92700 49100 92700 48900 4
+N 87200 49100 87200 49900 4
+N 87200 49900 88000 49900 4
+N 89900 49900 89900 49100 4
+N 88900 49900 90700 49900 4
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+N 92700 47800 92700 48000 4
+N 89900 47800 89900 48000 4
+N 88200 47800 93500 47800 4
+{
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+netname=VCMO
+}
+C 86900 46600 1 180 0 resistor-1.sym
+{
+T 86500 46700 5 10 1 1 0 0 1
+value=95.3
+T 86900 46600 5 10 0 1 180 0 1
+footprint=0603
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+refdes=R87
+}
+C 87400 46400 1 0 0 inductor-1.sym
+{
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+refdes=L2
+T 87400 46400 5 10 0 1 0 0 1
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+}
+C 89600 46600 1 180 0 resistor-1.sym
+{
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+}
+C 90100 46400 1 0 0 inductor-1.sym
+{
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+T 90100 46400 5 10 0 1 0 0 1
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+}
+C 92300 46600 1 180 0 resistor-1.sym
+{
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+footprint=0603
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+refdes=R6
+}
+C 88000 47500 1 180 1 capacitor-1.sym
+{
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+refdes=C88
+T 89000 47500 5 10 1 1 0 6 1
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+footprint=0603
+}
+C 90700 47500 1 180 1 capacitor-1.sym
+{
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+T 91300 47400 5 10 1 1 0 0 1
+value=8.2pF
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+footprint=0603
+}
+C 90100 46300 1 90 1 capacitor-1.sym
+{
+T 90000 46000 5 10 1 1 0 0 1
+refdes=C86
+T 90500 45500 5 10 1 1 0 6 1
+value=150pF
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+footprint=0603
+}
+C 92900 46300 1 90 1 capacitor-1.sym
+{
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+T 93300 45500 5 10 1 1 0 6 1
+value=82pF
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+footprint=0603
+}
+C 93600 45400 1 90 0 resistor-1.sym
+{
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+value=100
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+footprint=0603
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+refdes=R8
+}
+N 86900 46500 87400 46500 4
+N 88300 46500 88700 46500 4
+N 89600 46500 90100 46500 4
+N 89900 46500 89900 46300 4
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+N 93500 45400 93500 45200 4
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+N 89900 45200 89900 45400 4
+N 88200 45200 93500 45200 4
+{
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+}
+N 92300 46500 94100 46500 4
+N 94100 47500 94300 47500 4
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+N 85400 48200 83600 48200 4
+N 94100 47900 94100 49100 4
+N 94100 46500 94100 47500 4
+N 77300 33600 79300 33600 4
+{
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+netname=VCMO
+}
+C 73800 34000 1 0 0 generic-power.sym
+{
+T 74000 34250 5 10 1 1 180 5 1
+net=5V_RX:1
+}
+C 73900 32000 1 270 0 resistor-1.sym
+{
+T 73700 31800 5 10 1 1 270 0 1
+value=1K
+T 73900 32000 5 10 0 1 270 0 1
+footprint=0603
+T 74200 31700 5 10 1 1 270 0 1
+refdes=R11
+}
+C 73900 33400 1 270 0 resistor-1.sym
+{
+T 73700 33200 5 10 1 1 270 0 1
+value=1K
+T 73900 33400 5 10 0 1 270 0 1
+footprint=0603
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+refdes=R10
+}
+C 77500 31600 1 90 1 capacitor-1.sym
+{
+T 77400 31300 5 10 1 1 0 0 1
+refdes=C84
+T 77700 30800 5 10 1 1 0 6 1
+value=0.1uF
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+footprint=0603
+}
+N 74000 30500 74000 31100 4
+N 74000 32000 74000 32500 4
+N 74000 33400 74000 34000 4
+C 78000 31600 1 90 1 capacitor-1.sym
+{
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+refdes=C83
+T 78200 30800 5 10 1 1 0 6 1
+value=0.1uF
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+footprint=0603
+}
+C 78500 31600 1 90 1 capacitor-1.sym
+{
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+T 78700 30800 5 10 1 1 0 6 1
+value=0.1uF
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+footprint=0603
+}
+N 78300 31600 78300 32800 4
+N 78300 32800 79300 32800 4
+N 77800 31600 77800 33200 4
+N 77800 33200 79300 33200 4
+N 77300 31600 77300 34700 4
+C 78000 30300 1 180 0 generic-power.sym
+{
+T 77800 30050 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 77300 30700 77300 30500 4
+N 77800 30300 77800 30700 4
+N 77800 30500 78300 30500 4
+N 78300 30500 78300 30700 4
+N 80700 48600 81600 48600 4
+{
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+}
+N 80700 48200 81600 48200 4
+{
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+netname=LON
+}
+N 77400 46200 79400 46200 4
+{
+T 77600 46200 5 10 1 1 0 0 1
+netname=AUX_DAC_A_RX
+}
+C 79400 46300 1 180 1 resistor-1.sym
+{
+T 80100 46300 5 10 1 1 0 0 1
+value=0
+T 79400 46300 5 10 0 1 0 2 1
+footprint=0603
+T 79500 46300 5 10 1 1 0 0 1
+refdes=R95
+}
+C 79400 45900 1 180 1 resistor-1.sym
+{
+T 79800 46000 5 10 1 1 0 6 1
+value=NONE
+T 79400 45900 5 10 0 1 0 2 1
+footprint=0603
+T 80300 45600 5 10 1 1 0 6 1
+refdes=R96
+}
+N 78500 45800 79400 45800 4
+C 79200 45600 1 90 1 capacitor-1.sym
+{
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+refdes=C95
+T 79400 44800 5 10 1 1 0 6 1
+value=0.1uF
+T 79200 45600 5 10 0 1 180 2 1
+footprint=0603
+}
+C 78800 44600 1 180 1 generic-power.sym
+{
+T 79000 44350 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 79000 44600 79000 44700 4
+C 77600 45900 1 180 1 resistor-1.sym
+{
+T 77900 46100 5 10 1 1 180 6 1
+value=NONE
+T 77600 45900 5 10 0 1 0 2 1
+footprint=0603
+T 77800 45600 5 10 1 1 180 6 1
+refdes=R97
+}
+N 79000 45600 79000 45800 4
+N 76300 45800 77600 45800 4
+{
+T 76500 45800 5 10 1 1 0 0 1
+netname=io_rx_08
+}
+N 68200 42600 67900 42600 4
+C 80100 48000 1 180 1 capacitor-1.sym
+{
+T 80400 47900 5 10 1 1 0 6 1
+refdes=C94
+T 81300 47900 5 10 1 1 0 6 1
+value=1000pF
+T 80100 48000 5 10 0 1 270 2 1
+footprint=0603
+}
+C 80300 47600 1 180 1 capacitor-1.sym
+{
+T 80500 47500 5 10 1 1 0 6 1
+refdes=C93
+T 81500 47500 5 10 1 1 0 6 1
+value=1000pF
+T 80300 47600 5 10 0 1 270 2 1
+footprint=0603
+}
+N 81000 47800 81600 47800 4
+N 81600 47400 81200 47400 4
+C 79500 47600 1 270 1 resistor-1.sym
+{
+T 79400 48000 5 10 1 1 0 6 1
+value=57.6
+T 79500 47600 5 10 0 1 90 2 1
+footprint=0603
+T 79100 48200 5 10 1 1 0 0 1
+refdes=R18
+}
+C 79200 47600 1 90 1 generic-power.sym
+{
+T 78950 47400 5 10 1 1 90 3 1
+net=AGND:1
+}
+N 79200 47400 80300 47400 4
+N 80100 47800 79900 47800 4
+N 79600 48700 79600 48500 4
+N 79600 47600 79600 47400 4
+C 95300 35500 1 0 0 generic-power.sym
+{
+T 95500 35750 5 10 1 1 180 5 1
+net=5V_RX:1
+}
+N 95500 35100 95500 35500 4
+N 74800 48700 75200 48700 4
+T 68500 49400 9 10 1 0 0 0 6
+Max Gain
+22
+45.5
+-6
+20
+81.5
+T 70000 49400 9 10 1 0 0 0 6
+Min Gain
+22
+1.5
+-6
+0
+17.5
+T 66900 49400 9 10 1 0 0 0 6
+Stage
+LNA
+AD8348
+Filter
+AD9862 ADC
+Sum
+T 66900 49000 9 10 1 0 0 0 1
+At max gain, thermal noise will be approx 5% of max scale
+C 77400 48900 1 180 1 capacitor-1.sym
+{
+T 78000 48800 5 10 1 1 0 0 1
+refdes=C96
+T 78000 48600 5 10 1 1 180 6 1
+value=1000pF
+T 77400 48900 5 10 0 1 270 2 1
+footprint=0603
+}
+C 77100 49900 1 270 0 inductor-1.sym
+{
+T 77400 49800 5 10 1 1 0 0 1
+refdes=L98
+T 77100 49900 5 10 0 1 270 0 1
+footprint=0603
+T 77400 49100 5 10 1 1 0 0 1
+value=100nH
+}
+N 76900 48700 77400 48700 4
+N 77200 48700 77200 49000 4
+C 77900 50900 1 180 1 capacitor-1.sym
+{
+T 78500 50800 5 10 1 1 0 0 1
+refdes=C98
+T 78500 50600 5 10 1 1 180 6 1
+value=.01uF
+T 77900 50900 5 10 0 1 270 2 1
+footprint=0603
+}
+C 77900 50300 1 180 1 capacitor-1.sym
+{
+T 78500 50200 5 10 1 1 0 0 1
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+T 78500 50000 5 10 1 1 180 6 1
+value=100pF
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+footprint=0603
+}
+N 77200 50100 77900 50100 4
+N 77700 50100 77700 50700 4
+N 77700 50700 77900 50700 4
+C 79600 50200 1 270 1 generic-power.sym
+{
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+net=AGND:1
+}
+N 79600 50400 79300 50400 4
+N 79300 50700 78800 50700 4
+N 78800 50100 79300 50100 4
+N 79300 50100 79300 50700 4
+N 96500 38600 96500 41600 4
+C 78900 31800 1 90 0 generic-power.sym
+{
+T 78650 32000 5 10 1 1 270 5 1
+net=5V_RX:1
+}
+N 78900 32000 79300 32000 4
+C 79800 47800 1 270 1 resistor-1.sym
+{
+T 80100 48300 5 10 1 1 0 0 1
+value=174
+T 79800 47800 5 10 0 1 90 2 1
+footprint=0603
+T 80000 48500 5 10 1 1 0 0 1
+refdes=R14
+}
+C 80700 45700 1 90 1 capacitor-1.sym
+{
+T 80600 45400 5 10 1 1 0 0 1
+refdes=C33
+T 80900 44900 5 10 1 1 0 6 1
+value=0.1uF
+T 80700 45700 5 10 0 1 180 2 1
+footprint=0603
+}
+C 80300 44700 1 180 1 generic-power.sym
+{
+T 80500 44450 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 80500 44700 80500 44800 4
+N 80300 45800 80500 45800 4
+N 80300 46200 81600 46200 4
+N 80500 45700 80500 46200 4
+C 71400 44500 1 0 0 header16-1.sym
+{
+T 71900 47800 5 10 1 1 0 0 1
+refdes=J24
+T 71400 44500 5 10 0 1 0 0 1
+footprint=CONNECTOR16
+}
+N 72800 46300 73100 46300 4
+N 72800 47500 73000 47500 4
+N 73000 47500 73000 46300 4
+N 73000 46300 73000 44700 4
+N 73000 44700 72800 44700 4
+N 72800 47100 73000 47100 4
+N 72800 46700 73000 46700 4
+N 72800 45900 73000 45900 4
+N 72800 45500 73000 45500 4
+N 72800 45100 73000 45100 4
+N 69800 46700 71400 46700 4
+{
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+netname=io_rx_13
+}
+N 69800 47500 71400 47500 4
+{
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+netname=io_rx_15
+}
+N 69800 45900 71400 45900 4
+{
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+netname=io_rx_11
+}
+N 69800 45100 71400 45100 4
+{
+T 70200 45100 5 10 1 1 0 0 1
+netname=io_rx_09
+}
+N 69800 47100 71400 47100 4
+{
+T 70200 47100 5 10 1 1 0 0 1
+netname=io_rx_14
+}
+N 69800 45500 71400 45500 4
+{
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+netname=io_rx_10
+}
+N 69800 46300 71400 46300 4
+{
+T 70200 46300 5 10 1 1 0 0 1
+netname=io_rx_12
+}
+N 69800 44700 71400 44700 4
+{
+T 70200 44700 5 10 1 1 0 0 1
+netname=io_rx_08
+}
+T 66200 44500 9 15 1 0 0 0 10
+RX Nets
+refclk_rx
+SDO_RX
+lockdet_rx
+SCLK_RX
+SEN_RX
+RX Enable
+RX1 / RX2
+RX Power
+digital agc
+T 68300 44500 9 15 1 0 0 0 10
+Pin
+io_rx_00
+io_rx_01
+io_rx_02
+io_rx_03
+io_rx_04
+io_rx_05
+io_rx_06
+io_rx_07
+io_rx_08
+N 70800 36200 72200 36200 4
+{
+T 71200 36200 5 10 1 1 0 0 1
+netname=SEN_RX
+}
+N 70800 37400 72200 37400 4
+{
+T 71200 37400 5 10 1 1 0 0 1
+netname=SCLK_RX
+}
+N 70800 36600 72200 36600 4
+{
+T 71200 36600 5 10 1 1 0 0 1
+netname=SDO_RX
+}
+C 70800 37500 1 180 0 resistor-1.sym
+{
+T 70700 37500 5 10 1 1 0 0 1
+value=0
+T 70800 37500 5 10 0 1 180 0 1
+footprint=0603
+T 69900 37500 5 10 1 1 0 0 1
+refdes=R40
+}
+N 69900 37400 69600 37400 4
+C 73100 37500 1 180 0 resistor-1.sym
+{
+T 73000 37500 5 10 1 1 0 0 1
+value=None
+T 73100 37500 5 10 0 1 180 0 1
+footprint=0603
+T 72200 37500 5 10 1 1 0 0 1
+refdes=R43
+}
+C 73100 36700 1 180 0 resistor-1.sym
+{
+T 73000 36700 5 10 1 1 0 0 1
+value=None
+T 73100 36700 5 10 0 1 180 0 1
+footprint=0603
+T 72200 36700 5 10 1 1 0 0 1
+refdes=R44
+}
+N 74500 37400 73100 37400 4
+{
+T 74400 37400 5 10 1 1 0 6 1
+netname=io_rx_03
+}
+N 74500 36600 73100 36600 4
+{
+T 74400 36600 5 10 1 1 0 6 1
+netname=io_rx_01
+}
+C 70800 36300 1 180 0 resistor-1.sym
+{
+T 70700 36300 5 10 1 1 0 0 1
+value=0
+T 70800 36300 5 10 0 1 180 0 1
+footprint=0603
+T 69900 36300 5 10 1 1 0 0 1
+refdes=R42
+}
+N 69900 36200 69600 36200 4
+C 73100 36300 1 180 0 resistor-1.sym
+{
+T 73000 36300 5 10 1 1 0 0 1
+value=None
+T 73100 36300 5 10 0 1 180 0 1
+footprint=0603
+T 72200 36300 5 10 1 1 0 0 1
+refdes=R45
+}
+N 74500 36200 73100 36200 4
+{
+T 74400 36200 5 10 1 1 0 6 1
+netname=io_rx_04
+}
+C 70800 36700 1 180 0 resistor-1.sym
+{
+T 70700 36700 5 10 1 1 0 0 1
+value=0
+T 70800 36700 5 10 0 1 180 0 1
+footprint=0603
+T 69900 36700 5 10 1 1 0 0 1
+refdes=R46
+}
+N 69600 36600 69900 36600 4
+C 94200 46200 1 0 0 ad8348-OUT.sym
+{
+T 95200 48600 5 10 1 1 0 6 1
+refdes=U2
+}
+C 93400 34600 1 270 0 ad8348-PWR.sym
+{
+T 93900 34300 5 10 1 1 0 6 1
+refdes=U2
+}
+T 95700 43000 9 10 1 0 0 0 1
+Tune both for 840-900 MHz
+C 94800 41500 1 0 1 inductor-1.sym
+{
+T 94800 41800 5 10 1 1 0 6 1
+refdes=L31
+T 94800 41500 5 10 0 1 0 6 1
+footprint=0402
+T 94200 41800 5 10 1 1 0 6 1
+value=4.3nH
+}
+C 96100 41100 1 180 0 inductor-1.sym
+{
+T 96200 40800 5 10 1 1 180 0 1
+refdes=L32
+T 96100 41100 5 10 0 1 180 0 1
+footprint=0402
+T 95700 40800 5 10 1 1 180 0 1
+value=4.3nH
+}
+C 93900 41300 1 0 0 resistor-1.sym
+{
+T 94000 41300 5 10 1 1 180 0 1
+value=470
+T 93900 41300 5 10 0 1 0 0 1
+footprint=0402
+T 94800 41300 5 10 1 1 180 0 1
+refdes=R30
+}
+C 96100 41300 1 180 0 resistor-1.sym
+{
+T 96000 41300 5 10 1 1 0 0 1
+value=470
+T 96100 41300 5 10 0 1 180 0 1
+footprint=0402
+T 95200 41300 5 10 1 1 0 0 1
+refdes=R31
+}
+N 93900 41600 93400 41600 4
+N 93700 41600 93700 41400 4
+N 93700 41400 93900 41400 4
+N 94800 41400 94900 41400 4
+N 94900 41400 94900 41600 4
+N 94800 41600 96500 41600 4
+N 93400 41200 95200 41200 4
+N 95000 41200 95000 41000 4
+N 95000 41000 95200 41000 4
+N 96100 41000 96200 41000 4
+N 96200 41000 96200 41200 4
+N 96100 41200 96500 41200 4
+N 93700 39100 93700 40800 4
+N 93700 40800 93400 40800 4
+N 78300 48700 79900 48700 4
+C 76200 47400 1 180 0 generic-power.sym
+{
+T 76000 47150 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 75800 47700 76400 47700 4
+N 76400 47700 76400 48000 4
+N 76100 47700 76100 48000 4
+N 75800 47700 75800 48000 4
+N 76000 47400 76000 47700 4
+C 87200 41700 1 270 0 capacitor-1.sym
+{
+T 87400 41500 5 10 1 1 180 0 1
+refdes=C36
+T 87400 41000 5 10 1 1 0 6 1
+value=NONE
+T 87200 41700 5 10 0 1 0 0 1
+footprint=0603
+}
+N 87400 41700 87400 42600 4
+N 87400 40500 87400 40800 4
+N 87000 42200 87400 42200 4
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diff --git a/usrp-hw/rfx/rcv900.sch b/usrp-hw/rfx/rcv900.sch
new file mode 100644
index 000000000..e48510cf8
--- /dev/null
+++ b/usrp-hw/rfx/rcv900.sch
@@ -0,0 +1,2089 @@
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+T 90700 47500 5 10 0 1 270 2 1
+footprint=0603
+}
+C 90100 46300 1 90 1 capacitor-1.sym
+{
+T 90000 46000 5 10 1 1 0 0 1
+refdes=C86
+T 90500 45500 5 10 1 1 0 6 1
+value=150pF
+T 90100 46300 5 10 0 1 180 2 1
+footprint=0603
+}
+C 92900 46300 1 90 1 capacitor-1.sym
+{
+T 92800 46000 5 10 1 1 0 0 1
+refdes=C85
+T 93300 45500 5 10 1 1 0 6 1
+value=82pF
+T 92900 46300 5 10 0 1 180 2 1
+footprint=0603
+}
+C 93600 45400 1 90 0 resistor-1.sym
+{
+T 93700 45700 5 10 1 1 0 0 1
+value=100
+T 93600 45400 5 10 0 1 90 0 1
+footprint=0603
+T 93700 46000 5 10 1 1 0 0 1
+refdes=R8
+}
+N 86900 46500 87400 46500 4
+N 88300 46500 88700 46500 4
+N 89600 46500 90100 46500 4
+N 89900 46500 89900 46300 4
+N 91000 46500 91400 46500 4
+N 93500 46500 93500 46300 4
+N 92700 46500 92700 46300 4
+N 87200 46500 87200 47300 4
+N 87200 47300 88000 47300 4
+N 89900 47300 89900 46500 4
+N 88900 47300 90700 47300 4
+N 91600 47300 92700 47300 4
+N 92700 47300 92700 46500 4
+N 93500 45400 93500 45200 4
+N 92700 45200 92700 45400 4
+N 89900 45200 89900 45400 4
+N 88200 45200 93500 45200 4
+{
+T 88400 45200 5 10 1 1 0 0 1
+netname=vref_rx
+}
+N 92300 46500 94100 46500 4
+N 84400 47500 94300 47500 4
+N 92300 49100 94100 49100 4
+N 94100 47900 94300 47900 4
+N 83600 48200 85400 48200 4
+N 85400 48200 85400 49100 4
+N 85400 49100 86000 49100 4
+N 86000 46500 85400 46500 4
+N 85400 46500 85400 47800 4
+N 85400 47800 83600 47800 4
+N 94100 47900 94100 49100 4
+N 94100 46500 94100 47500 4
+N 77300 33600 79300 33600 4
+C 73800 34000 1 0 0 generic-power.sym
+{
+T 74000 34250 5 10 1 1 180 5 1
+net=5V_RX:1
+}
+C 73900 32000 1 270 0 resistor-1.sym
+{
+T 73700 31800 5 10 1 1 270 0 1
+value=1K
+T 73900 32000 5 10 0 1 270 0 1
+footprint=0603
+T 74200 31700 5 10 1 1 270 0 1
+refdes=R11
+}
+C 73900 33400 1 270 0 resistor-1.sym
+{
+T 73700 33200 5 10 1 1 270 0 1
+value=2K
+T 73900 33400 5 10 0 1 270 0 1
+footprint=0603
+T 74200 33100 5 10 1 1 270 0 1
+refdes=R10
+}
+C 77500 31600 1 90 1 capacitor-1.sym
+{
+T 77400 31300 5 10 1 1 0 0 1
+refdes=C84
+T 77700 30800 5 10 1 1 0 6 1
+value=0.1uF
+T 77500 31600 5 10 0 1 180 2 1
+footprint=0603
+}
+N 74000 30500 74000 31100 4
+N 74000 32000 74000 32500 4
+N 74000 33400 74000 34000 4
+C 78000 31600 1 90 1 capacitor-1.sym
+{
+T 77900 31300 5 10 1 1 0 0 1
+refdes=C83
+T 78200 30800 5 10 1 1 0 6 1
+value=0.1uF
+T 78000 31600 5 10 0 1 180 2 1
+footprint=0603
+}
+C 78500 31600 1 90 1 capacitor-1.sym
+{
+T 78400 31300 5 10 1 1 0 0 1
+refdes=C82
+T 78700 30800 5 10 1 1 0 6 1
+value=0.1uF
+T 78500 31600 5 10 0 1 180 2 1
+footprint=0603
+}
+N 78300 31600 78300 32800 4
+N 78300 32800 79300 32800 4
+N 77800 31600 77800 33200 4
+N 77800 33200 79300 33200 4
+N 77300 31600 77300 34700 4
+C 78000 30300 1 180 0 generic-power.sym
+{
+T 77800 30050 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 77300 30700 77300 30500 4
+N 77800 30300 77800 30700 4
+N 77800 30500 78300 30500 4
+N 78300 30500 78300 30700 4
+N 80700 48600 81600 48600 4
+{
+T 80900 48600 5 10 1 1 0 0 1
+netname=LON
+}
+N 77400 47000 79400 47000 4
+{
+T 77600 47000 5 10 1 1 0 0 1
+netname=AUX_DAC_A_RX
+}
+C 79400 47100 1 180 1 resistor-1.sym
+{
+T 80100 47100 5 10 1 1 0 0 1
+value=0
+T 79400 47100 5 10 0 1 0 2 1
+footprint=0603
+T 79500 47100 5 10 1 1 0 0 1
+refdes=R95
+}
+C 79400 46700 1 180 1 resistor-1.sym
+{
+T 79800 46800 5 10 1 1 0 6 1
+value=NONE
+T 79400 46700 5 10 0 1 0 2 1
+footprint=0603
+T 80300 46400 5 10 1 1 0 6 1
+refdes=R96
+}
+N 78500 46600 79400 46600 4
+C 79200 46400 1 90 1 capacitor-1.sym
+{
+T 79100 46100 5 10 1 1 0 0 1
+refdes=C95
+T 79400 45600 5 10 1 1 0 6 1
+value=0.1uF
+T 79200 46400 5 10 0 1 180 2 1
+footprint=0603
+}
+C 78800 45400 1 180 1 generic-power.sym
+{
+T 79000 45150 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 79000 45400 79000 45500 4
+C 77600 46700 1 180 1 resistor-1.sym
+{
+T 77900 46900 5 10 1 1 180 6 1
+value=NONE
+T 77600 46700 5 10 0 1 0 2 1
+footprint=0603
+T 77800 46400 5 10 1 1 180 6 1
+refdes=R97
+}
+N 79000 46400 79000 46600 4
+N 76300 46600 77600 46600 4
+{
+T 76500 46600 5 10 1 1 0 0 1
+netname=io_rx_08
+}
+N 68200 42600 67900 42600 4
+C 80100 48000 1 180 1 capacitor-1.sym
+{
+T 80400 47900 5 10 1 1 0 6 1
+refdes=C94
+T 81300 47900 5 10 1 1 0 6 1
+value=220pF
+T 80100 48000 5 10 0 1 270 2 1
+footprint=0603
+}
+C 80300 47600 1 180 1 capacitor-1.sym
+{
+T 80500 47500 5 10 1 1 0 6 1
+refdes=C93
+T 81500 47500 5 10 1 1 0 6 1
+value=220pF
+T 80300 47600 5 10 0 1 270 2 1
+footprint=0603
+}
+N 81000 47800 81600 47800 4
+N 81600 47400 81200 47400 4
+C 79500 47600 1 270 1 resistor-1.sym
+{
+T 79400 48000 5 10 1 1 0 6 1
+value=200
+T 79500 47600 5 10 0 1 90 2 1
+footprint=0603
+T 79100 48200 5 10 1 1 0 0 1
+refdes=R18
+}
+C 79200 47600 1 90 1 generic-power.sym
+{
+T 78950 47400 5 10 1 1 90 3 1
+net=AGND:1
+}
+N 79200 47400 80300 47400 4
+N 80100 47800 79900 47800 4
+N 79600 48700 79600 48500 4
+N 79600 47600 79600 47400 4
+C 94300 35500 1 0 0 generic-power.sym
+{
+T 94500 35750 5 10 1 1 180 5 1
+net=5V_RX:1
+}
+N 94500 35100 94500 35500 4
+T 68500 49400 9 10 1 0 0 0 6
+Max Gain
+22
+45.5
+-6
+20
+81.5
+T 70000 49400 9 10 1 0 0 0 6
+Min Gain
+22
+1.5
+-6
+0
+17.5
+T 66900 49400 9 10 1 0 0 0 6
+Stage
+LNA
+AD8348
+Filter
+AD9862 ADC
+Sum
+T 66900 49000 9 10 1 0 0 0 1
+At max gain, thermal noise will be approx 5% of max scale
+C 77400 48900 1 180 1 capacitor-1.sym
+{
+T 78000 48800 5 10 1 1 0 0 1
+refdes=C96
+T 78000 48600 5 10 1 1 180 6 1
+value=220pF
+T 77400 48900 5 10 0 1 270 2 1
+footprint=0603
+}
+C 77100 49900 1 270 0 inductor-1.sym
+{
+T 77400 49600 5 10 1 1 0 0 1
+refdes=L98
+T 77100 49900 5 10 0 1 270 0 1
+footprint=0603
+T 77400 49400 5 10 1 1 0 0 1
+value=100nH
+}
+N 76900 48700 77400 48700 4
+N 77200 48700 77200 49000 4
+C 77900 50900 1 180 1 capacitor-1.sym
+{
+T 78500 50800 5 10 1 1 0 0 1
+refdes=C98
+T 78500 50600 5 10 1 1 180 6 1
+value=0.1uF
+T 77900 50900 5 10 0 1 270 2 1
+footprint=0603
+}
+C 77900 50300 1 180 1 capacitor-1.sym
+{
+T 78500 50200 5 10 1 1 0 0 1
+refdes=C97
+T 78500 50000 5 10 1 1 180 6 1
+value=220pF
+T 77900 50300 5 10 0 1 270 2 1
+footprint=0603
+}
+N 76900 50100 77900 50100 4
+N 77700 50100 77700 50700 4
+N 77700 50700 77900 50700 4
+C 79600 50200 1 270 1 generic-power.sym
+{
+T 79850 50400 5 10 1 1 270 3 1
+net=AGND:1
+}
+N 79600 50400 79300 50400 4
+N 79300 50700 78800 50700 4
+N 78800 50100 79300 50100 4
+N 79300 50100 79300 50700 4
+N 96500 38600 96500 41600 4
+C 80700 46500 1 90 1 capacitor-1.sym
+{
+T 80600 46200 5 10 1 1 0 0 1
+refdes=C33
+T 80900 45700 5 10 1 1 0 6 1
+value=0.1uF
+T 80700 46500 5 10 0 1 180 2 1
+footprint=0603
+}
+C 80300 45500 1 180 1 generic-power.sym
+{
+T 80500 45250 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 80500 45500 80500 45600 4
+N 80300 46600 80500 46600 4
+N 80300 47000 81600 47000 4
+N 80500 46500 80500 47000 4
+C 71400 44500 1 0 0 header16-1.sym
+{
+T 71900 47800 5 10 1 1 0 0 1
+refdes=J24
+T 71400 44500 5 10 0 1 0 0 1
+footprint=CONNECTOR16
+}
+N 72800 46300 73100 46300 4
+N 72800 47500 73000 47500 4
+N 73000 47500 73000 46300 4
+N 73000 46300 73000 44700 4
+N 73000 44700 72800 44700 4
+N 72800 47100 73000 47100 4
+N 72800 46700 73000 46700 4
+N 72800 45900 73000 45900 4
+N 72800 45500 73000 45500 4
+N 72800 45100 73000 45100 4
+N 69800 46700 71400 46700 4
+{
+T 70200 46700 5 10 1 1 0 0 1
+netname=io_rx_13
+}
+N 69800 47500 71400 47500 4
+{
+T 70200 47500 5 10 1 1 0 0 1
+netname=io_rx_15
+}
+N 69800 45900 71400 45900 4
+{
+T 70200 45900 5 10 1 1 0 0 1
+netname=io_rx_11
+}
+N 69800 45100 71400 45100 4
+{
+T 70200 45100 5 10 1 1 0 0 1
+netname=io_rx_09
+}
+N 69800 47100 71400 47100 4
+{
+T 70200 47100 5 10 1 1 0 0 1
+netname=io_rx_14
+}
+N 69800 45500 71400 45500 4
+{
+T 70200 45500 5 10 1 1 0 0 1
+netname=io_rx_10
+}
+N 69800 46300 71400 46300 4
+{
+T 70200 46300 5 10 1 1 0 0 1
+netname=io_rx_12
+}
+N 69800 44700 71400 44700 4
+{
+T 70200 44700 5 10 1 1 0 0 1
+netname=io_rx_08
+}
+T 66200 44500 9 15 1 0 0 0 10
+RX Nets
+refclk_rx
+SDO_RX
+lockdet_rx
+SCLK_RX
+SEN_RX
+RX Enable
+RX1 / RX2
+RX Power
+digital agc
+T 68300 44500 9 15 1 0 0 0 10
+Pin
+io_rx_00
+io_rx_01
+io_rx_02
+io_rx_03
+io_rx_04
+io_rx_05
+io_rx_06
+io_rx_07
+io_rx_08
+N 70800 36200 72200 36200 4
+{
+T 71200 36200 5 10 1 1 0 0 1
+netname=SEN_RX
+}
+N 70800 37400 72200 37400 4
+{
+T 71200 37400 5 10 1 1 0 0 1
+netname=SCLK_RX
+}
+N 70800 36600 72200 36600 4
+{
+T 71200 36600 5 10 1 1 0 0 1
+netname=SDO_RX
+}
+C 70800 37500 1 180 0 resistor-1.sym
+{
+T 70700 37500 5 10 1 1 0 0 1
+value=0
+T 70800 37500 5 10 0 1 180 0 1
+footprint=0603
+T 69900 37500 5 10 1 1 0 0 1
+refdes=R40
+}
+N 69900 37400 69600 37400 4
+C 73100 37500 1 180 0 resistor-1.sym
+{
+T 73000 37500 5 10 1 1 0 0 1
+value=None
+T 73100 37500 5 10 0 1 180 0 1
+footprint=0603
+T 72200 37500 5 10 1 1 0 0 1
+refdes=R43
+}
+C 73100 36700 1 180 0 resistor-1.sym
+{
+T 73000 36700 5 10 1 1 0 0 1
+value=None
+T 73100 36700 5 10 0 1 180 0 1
+footprint=0603
+T 72200 36700 5 10 1 1 0 0 1
+refdes=R44
+}
+N 74500 37400 73100 37400 4
+{
+T 74400 37400 5 10 1 1 0 6 1
+netname=io_rx_03
+}
+N 74500 36600 73100 36600 4
+{
+T 74400 36600 5 10 1 1 0 6 1
+netname=io_rx_01
+}
+C 70800 36300 1 180 0 resistor-1.sym
+{
+T 70700 36300 5 10 1 1 0 0 1
+value=0
+T 70800 36300 5 10 0 1 180 0 1
+footprint=0603
+T 69900 36300 5 10 1 1 0 0 1
+refdes=R42
+}
+N 69900 36200 69600 36200 4
+C 73100 36300 1 180 0 resistor-1.sym
+{
+T 73000 36300 5 10 1 1 0 0 1
+value=None
+T 73100 36300 5 10 0 1 180 0 1
+footprint=0603
+T 72200 36300 5 10 1 1 0 0 1
+refdes=R45
+}
+N 74500 36200 73100 36200 4
+{
+T 74400 36200 5 10 1 1 0 6 1
+netname=io_rx_04
+}
+C 70800 36700 1 180 0 resistor-1.sym
+{
+T 70700 36700 5 10 1 1 0 0 1
+value=0
+T 70800 36700 5 10 0 1 180 0 1
+footprint=0603
+T 69900 36700 5 10 1 1 0 0 1
+refdes=R46
+}
+N 69600 36600 69900 36600 4
+T 95700 43000 9 10 1 0 0 0 1
+Tune both for 840-900 MHz
+N 93400 41600 96500 41600 4
+N 93400 41200 96500 41200 4
+N 93700 39100 93700 40800 4
+N 93700 40800 93400 40800 4
+N 78300 48700 79900 48700 4
+C 76200 47400 1 180 0 generic-power.sym
+{
+T 76000 47150 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 76400 47700 76400 48000 4
+N 76100 47700 76100 48000 4
+N 75800 47700 75800 48000 4
+N 76000 47400 76000 47700 4
+C 87200 41700 1 270 0 capacitor-1.sym
+{
+T 87400 41500 5 10 1 1 180 0 1
+refdes=C36
+T 87400 41000 5 10 1 1 0 6 1
+value=NONE
+T 87200 41700 5 10 0 1 0 0 1
+footprint=0603
+}
+N 87400 41700 87400 42600 4
+N 87400 40500 87400 40800 4
+N 87000 42200 87400 42200 4
+C 91700 37000 1 0 1 connector2-1.sym
+{
+T 91700 37800 5 10 1 1 0 6 1
+refdes=J3
+T 91700 37000 5 10 0 1 0 6 1
+footprint=CONNECTOR2
+}
+C 89900 37000 1 180 0 generic-power.sym
+{
+T 89700 36750 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 89700 37000 89700 37200 4
+N 89700 37200 90000 37200 4
+N 77900 32400 79300 32400 4
+{
+T 78400 32400 5 10 1 1 0 0 1
+netname=io_rx_05
+}
+C 97600 48000 1 180 0 resistor-1.sym
+{
+T 97500 48000 5 10 1 1 0 0 1
+value=200
+T 97600 48000 5 10 0 1 180 0 1
+footprint=0603
+T 96700 48000 5 10 1 1 0 0 1
+refdes=R47
+}
+C 97600 47600 1 180 0 resistor-1.sym
+{
+T 97500 47600 5 10 1 1 0 0 1
+value=200
+T 97600 47600 5 10 0 1 180 0 1
+footprint=0603
+T 96700 47600 5 10 1 1 0 0 1
+refdes=R48
+}
+C 97600 47200 1 180 0 resistor-1.sym
+{
+T 97500 47200 5 10 1 1 0 0 1
+value=200
+T 97600 47200 5 10 0 1 180 0 1
+footprint=0603
+T 96700 47200 5 10 1 1 0 0 1
+refdes=R49
+}
+C 97600 46800 1 180 0 resistor-1.sym
+{
+T 97500 46800 5 10 1 1 0 0 1
+value=200
+T 97600 46800 5 10 0 1 180 0 1
+footprint=0603
+T 96700 46800 5 10 1 1 0 0 1
+refdes=R50
+}
+N 96300 47900 96700 47900 4
+N 96300 47500 96700 47500 4
+N 96300 47100 96700 47100 4
+N 96300 46700 96700 46700 4
+C 67600 42800 1 90 0 generic-power.sym
+{
+T 67350 43000 5 10 1 1 90 3 1
+net=DGND_RX:1
+}
+C 67900 42400 1 90 0 generic-power.sym
+{
+T 67650 42600 5 10 1 1 90 3 1
+net=DGND_RX:1
+}
+C 69900 43200 1 270 0 generic-power.sym
+{
+T 70150 43000 5 10 1 1 270 3 1
+net=DGND_RX:1
+}
+C 69800 36000 1 270 0 generic-power.sym
+{
+T 70050 35800 5 10 1 1 270 3 1
+net=DGND_RX:1
+}
+C 68000 35600 1 90 0 generic-power.sym
+{
+T 67750 35800 5 10 1 1 90 3 1
+net=DGND_RX:1
+}
+C 73100 46500 1 270 0 generic-power.sym
+{
+T 73350 46300 5 10 1 1 270 3 1
+net=DGND_RX:1
+}
+C 86000 31300 1 270 0 generic-power.sym
+{
+T 86250 31100 5 10 1 1 270 3 1
+net=DGND_RX:1
+}
+N 74000 30500 77800 30500 4
+C 94000 43800 1 0 0 generic-power.sym
+{
+T 94200 44050 5 10 1 1 180 5 1
+net=3_3V_SYN_RX:1
+}
+N 94200 43600 94200 43800 4
+C 89900 41800 1 90 0 generic-power.sym
+{
+T 89650 42000 5 10 1 1 270 5 1
+net=3_3V_SYN_RX:1
+}
+C 75500 37800 1 90 1 capacitor-1.sym
+{
+T 75700 37700 5 10 1 1 0 6 1
+refdes=C32
+T 75400 37500 5 10 1 1 0 0 1
+value=220pF
+T 75500 37800 5 10 0 1 0 6 1
+footprint=0603
+}
+N 75300 36600 75300 36900 4
+C 78000 37800 1 270 0 capacitor-2.sym
+{
+T 77700 37000 5 10 1 1 0 0 1
+refdes=C6
+T 77700 36800 5 10 1 1 0 0 1
+value=4.7uF
+T 78000 37800 5 10 0 1 0 0 1
+footprint=1206
+}
+C 78600 36300 1 0 0 adp3336.sym
+{
+T 80300 38500 5 10 1 1 0 6 1
+refdes=U5
+}
+N 80700 37200 80900 37200 4
+N 80900 37200 80900 38000 4
+N 80900 37600 80700 37600 4
+C 80900 38500 1 0 0 generic-power.sym
+{
+T 81100 38750 5 10 1 1 0 3 1
+net=3_3V_SYN_RX:1
+}
+N 80700 38000 81100 38000 4
+C 75800 37800 1 270 0 capacitor-1.sym
+{
+T 75500 37000 5 10 1 1 0 0 1
+refdes=C34
+T 75500 36800 5 10 1 1 0 0 1
+value=0.1uF
+T 75800 37800 5 10 0 1 0 0 1
+footprint=0603
+}
+C 76700 37800 1 90 1 capacitor-1.sym
+{
+T 76900 37000 5 10 1 1 0 6 1
+refdes=C46
+T 76900 36800 5 10 1 1 0 6 1
+value=1uF
+T 76700 37800 5 10 0 1 0 6 1
+footprint=0603
+}
+N 76500 36600 76500 36900 4
+N 76500 37800 76500 38100 4
+N 76000 36600 76000 36900 4
+N 76000 37800 76000 38100 4
+C 76600 38000 1 0 0 inductor-1.sym
+{
+T 76800 38300 5 10 1 1 0 0 1
+refdes=L5
+T 76600 38000 5 10 0 1 0 0 1
+footprint=1206
+}
+C 77400 37800 1 270 0 capacitor-1.sym
+{
+T 77100 37000 5 10 1 1 0 0 1
+refdes=C45
+T 77100 36800 5 10 1 1 0 0 1
+value=0.1uF
+T 77400 37800 5 10 0 1 0 0 1
+footprint=0603
+}
+N 78200 36600 78200 36900 4
+N 78200 37800 78200 38100 4
+N 77600 36600 77600 36900 4
+N 77600 37800 77600 38100 4
+N 76000 36200 76000 36600 4
+N 77500 38100 78500 38100 4
+N 78500 37600 78700 37600 4
+N 78500 38000 78700 38000 4
+N 78400 37200 78700 37200 4
+N 78500 37600 78500 38100 4
+N 75300 36600 78500 36600 4
+N 78500 36600 78500 36800 4
+N 78500 36800 78700 36800 4
+C 81000 37800 1 270 0 resistor-1.sym
+{
+T 81300 37400 5 10 1 1 180 8 1
+refdes=R62
+T 81000 37800 5 10 0 1 90 8 1
+footprint=0603
+T 81300 37200 5 10 1 1 0 0 1
+value=140K
+}
+C 81000 36700 1 270 0 resistor-1.sym
+{
+T 81300 36300 5 10 1 1 180 8 1
+refdes=R80
+T 81000 36700 5 10 0 1 90 8 1
+footprint=0603
+T 81300 36100 5 10 1 1 0 0 1
+value=78.7K
+}
+N 81100 35700 81100 35800 4
+N 80700 36800 81100 36800 4
+N 81100 36700 81100 36900 4
+N 81100 37800 81100 38500 4
+C 82000 37900 1 90 1 capacitor-1.sym
+{
+T 81900 37600 5 10 1 1 0 0 1
+refdes=C1
+T 81900 37200 5 10 1 1 0 0 1
+value=470pF
+T 82000 37900 5 10 0 1 0 6 1
+footprint=0603
+}
+N 81100 36800 81800 36800 4
+N 81800 36800 81800 37000 4
+N 81100 38000 81800 38000 4
+N 81800 38000 81800 37900 4
+N 75300 38100 76600 38100 4
+C 76200 36200 1 180 0 generic-power.sym
+{
+T 76000 35950 5 10 1 1 180 3 1
+net=AGND:1
+}
+C 81300 35700 1 180 0 generic-power.sym
+{
+T 81100 35450 5 10 1 1 180 3 1
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diff --git a/usrp-hw/rfx/trans.sch b/usrp-hw/rfx/trans.sch
new file mode 100644
index 000000000..f90024ad7
--- /dev/null
+++ b/usrp-hw/rfx/trans.sch
@@ -0,0 +1,1789 @@
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diff --git a/usrp-hw/rfx/trans2400.sch b/usrp-hw/rfx/trans2400.sch
new file mode 100644
index 000000000..6783acb6b
--- /dev/null
+++ b/usrp-hw/rfx/trans2400.sch
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
+T 72000 30100 9 15 1 0 0 0 9
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+refclk_tx
+SDO_TX
+lockdet_tx
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+TX Power
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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diff --git a/usrp-hw/rfx/trans400.sch b/usrp-hw/rfx/trans400.sch
new file mode 100644
index 000000000..8c22fd8cb
--- /dev/null
+++ b/usrp-hw/rfx/trans400.sch
@@ -0,0 +1,1835 @@
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+}
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+}
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+}
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+}
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+}
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+{
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+}
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+{
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+}
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+}
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+}
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+{
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+}
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+{
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+}
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+{
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+}
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+{
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+}
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+{
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+}
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+{
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+}
+C 94600 38700 1 180 1 capacitor-1.sym
+{
+T 95200 38400 5 10 1 1 180 6 1
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+}
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+{
+T 95400 39200 5 10 1 1 0 0 1
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+}
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+{
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+}
+N 90800 40600 90400 40600 4
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+{
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+net=AGND:1
+}
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+{
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+}
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+{
+T 89800 41500 5 10 1 1 0 6 1
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+}
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+{
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+}
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+{
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+}
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+{
+T 87500 42100 5 10 1 1 0 6 1
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+value=.01uF
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+}
+C 88200 41700 1 270 0 resistor-1.sym
+{
+T 87900 41200 5 10 1 1 0 0 1
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+}
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+{
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+}
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+{
+T 73000 49600 5 10 1 1 0 6 1
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+}
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+{
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+}
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+{
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+}
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+{
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+}
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+{
+T 70500 50100 5 10 1 1 180 0 1
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+}
+C 70600 49300 1 270 0 resistor-1.sym
+{
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+}
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+{
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+value=10 1%
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+refdes=R103
+}
+N 70700 49400 70900 49400 4
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+{
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+net=AGND:1
+}
+N 72000 49200 72000 49400 4
+N 72000 49400 71800 49400 4
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+{
+T 76000 49400 5 10 1 1 180 0 1
+value=100 1%
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+}
+N 75200 48300 75200 49000 4
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+}
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+netname=IOUTN_B
+}
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+{
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+}
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+{
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+}
+C 72500 44900 1 0 0 inductor-1.sym
+{
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+}
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+{
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+}
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+{
+T 70200 46800 5 10 1 1 180 0 1
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+}
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+{
+T 70200 45700 5 10 1 1 180 0 1
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+}
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+{
+T 70800 46300 5 10 1 1 0 0 1
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+T 70800 45800 5 10 1 1 0 0 1
+refdes=R110
+}
+N 70400 46100 70600 46100 4
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+{
+T 71700 45650 5 10 1 1 180 3 1
+net=AGND:1
+}
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+N 71700 46100 71500 46100 4
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+{
+T 75400 46100 5 10 1 1 180 0 1
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+T 74800 46200 5 10 1 1 0 0 1
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+}
+N 74600 45000 74600 45700 4
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+net=5V_TX:1
+}
+N 96800 35000 96800 35300 4
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+{
+T 87800 48900 5 10 1 1 0 0 1
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+}
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+{
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+}
+N 78000 46300 76200 46300 4
+{
+T 76400 46300 5 10 1 1 0 0 1
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+}
+C 80600 48500 1 180 1 capacitor-1.sym
+{
+T 80900 48400 5 10 1 1 0 6 1
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+}
+C 84600 48500 1 180 1 capacitor-1.sym
+{
+T 84900 48400 5 10 1 1 0 6 1
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+}
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+{
+T 89900 48400 5 10 1 1 0 6 1
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+}
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+{
+T 84400 49000 5 10 1 1 0 0 1
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+}
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+}
+N 80000 48300 80600 48300 4
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+{
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+}
+C 86000 49300 1 180 0 generic-power.sym
+{
+T 85800 49050 5 10 1 1 180 3 1
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+}
+C 83100 47000 1 180 0 generic-power.sym
+{
+T 82900 46750 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 83000 47300 83000 47600 4
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+{
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+}
+N 88100 47000 88100 47600 4
+N 87900 47300 87900 47600 4
+N 87900 47300 88100 47300 4
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+{
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+}
+C 86000 48500 1 180 1 capacitor-1.sym
+{
+T 86300 48400 5 10 1 1 0 6 1
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+T 86300 48000 5 10 1 1 0 6 1
+value=15pF
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+footprint=0603
+}
+C 85900 46900 1 180 0 generic-power.sym
+{
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+}
+N 85500 48300 86000 48300 4
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+N 86900 48300 87200 48300 4
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+{
+T 89500 49000 5 10 1 1 0 0 1
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+}
+N 89300 50500 89300 49500 4
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+{
+T 90300 49800 5 10 1 1 0 6 1
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+}
+C 91300 49300 1 180 0 generic-power.sym
+{
+T 91100 49050 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 91100 49700 90900 49700 4
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+{
+T 90300 50400 5 10 1 1 0 6 1
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+}
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+N 91100 49300 91100 50300 4
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+{
+T 91000 47600 5 10 1 1 0 0 1
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+value=100nH
+}
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+{
+T 90800 46750 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 90800 47000 90800 47200 4
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+N 89300 48600 89300 48300 4
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+N 90000 50300 89300 50300 4
+N 90500 48300 92500 48300 4
+{
+T 91500 48300 5 10 1 1 0 0 1
+netname=RF_TX
+}
+T 72000 30100 9 15 1 0 0 0 9
+TX Nets
+refclk_tx
+SDO_TX
+lockdet_tx
+SCLK_TX
+SEN_TX
+TX Enable
+TX / RX
+TX Power
+C 71000 37400 1 180 0 resistor-1.sym
+{
+T 70900 37400 5 10 1 1 0 0 1
+value=0
+T 71000 37400 5 10 0 1 180 0 1
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+T 70100 37400 5 10 1 1 0 0 1
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+}
+N 70100 37300 69800 37300 4
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+{
+T 73200 37400 5 10 1 1 0 0 1
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+T 73300 37400 5 10 0 1 180 0 1
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+T 72400 37400 5 10 1 1 0 0 1
+refdes=R133
+}
+C 73300 36600 1 180 0 resistor-1.sym
+{
+T 73200 36600 5 10 1 1 0 0 1
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+T 73300 36600 5 10 0 1 180 0 1
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+T 72400 36600 5 10 1 1 0 0 1
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+}
+N 74700 37300 73300 37300 4
+{
+T 74600 37300 5 10 1 1 0 6 1
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+}
+N 74700 36500 73300 36500 4
+{
+T 74600 36500 5 10 1 1 0 6 1
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+}
+T 74200 30100 9 15 1 0 0 0 9
+Pin
+io_tx_00
+io_tx_01
+io_tx_02
+io_tx_03
+io_tx_04
+io_tx_05
+io_tx_06
+io_tx_07
+C 71000 36200 1 180 0 resistor-1.sym
+{
+T 70900 36200 5 10 1 1 0 0 1
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+T 71000 36200 5 10 0 1 180 0 1
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+T 70100 36200 5 10 1 1 0 0 1
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+}
+N 70100 36100 69800 36100 4
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+{
+T 73200 36200 5 10 1 1 0 0 1
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+T 73300 36200 5 10 0 1 180 0 1
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+T 72400 36200 5 10 1 1 0 0 1
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+}
+N 74700 36100 73300 36100 4
+{
+T 74600 36100 5 10 1 1 0 6 1
+netname=io_tx_04
+}
+C 77800 30000 1 0 0 header16-1.sym
+{
+T 78300 33300 5 10 1 1 0 0 1
+refdes=J101
+T 77800 30000 5 10 0 1 0 0 1
+footprint=CONNECTOR16
+}
+N 79200 31800 79500 31800 4
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+N 79400 33000 79400 31800 4
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+N 76200 32200 77800 32200 4
+{
+T 76600 32200 5 10 1 1 0 0 1
+netname=io_tx_13
+}
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diff --git a/usrp-hw/rfx/trans900.sch b/usrp-hw/rfx/trans900.sch
new file mode 100644
index 000000000..2e03fd9ba
--- /dev/null
+++ b/usrp-hw/rfx/trans900.sch
@@ -0,0 +1,1799 @@
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+}
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+}
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+}
+C 87000 40000 1 180 0 generic-power.sym
+{
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+net=AGND:1
+}
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+{
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+footprint=VCTCXO
+}
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+{
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+}
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+}
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+}
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+}
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+}
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+}
+C 82300 50700 1 0 0 generic-power.sym
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+net=3_3V_SYN_TX:1
+}
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+value=.01uF
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+}
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+{
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+footprint=0603
+}
+N 87000 48300 87200 48300 4
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+NOTE: INDUCTOR
diff --git a/usrp-hw/tvrx/ChangeLog b/usrp-hw/tvrx/ChangeLog
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/usrp-hw/tvrx/ChangeLog
diff --git a/usrp-hw/tvrx/gnetlistrc b/usrp-hw/tvrx/gnetlistrc
new file mode 100644
index 000000000..6bbd9c292
--- /dev/null
+++ b/usrp-hw/tvrx/gnetlistrc
@@ -0,0 +1,3 @@
+(component-library "../sym")
+(component-library "../sym/generated")
+
diff --git a/usrp-hw/tvrx/gschemrc b/usrp-hw/tvrx/gschemrc
new file mode 100644
index 000000000..6bbd9c292
--- /dev/null
+++ b/usrp-hw/tvrx/gschemrc
@@ -0,0 +1,3 @@
+(component-library "../sym")
+(component-library "../sym/generated")
+
diff --git a/usrp-hw/tvrx/netlist_cmd b/usrp-hw/tvrx/netlist_cmd
new file mode 100755
index 000000000..c22fad425
--- /dev/null
+++ b/usrp-hw/tvrx/netlist_cmd
@@ -0,0 +1,3 @@
+gsch2pcb tvrx.prj
+gnetlist -g partslist3 -o tvrx.bom tvrx.sch
+
diff --git a/usrp-hw/tvrx/tvrx.pcb b/usrp-hw/tvrx/tvrx.pcb
new file mode 100644
index 000000000..58f7cf27b
--- /dev/null
+++ b/usrp-hw/tvrx/tvrx.pcb
@@ -0,0 +1,2270 @@
+# release: pcb-bin 1.99p
+# date:    Mon Feb 28 17:13:08 2005
+# user:    matt (Matt Ettus)
+# host:    localhost.localdomain
+
+PCB["RX Daughterboard" 330000 250000]
+
+Grid[500.00000000 0 0 1]
+Cursor[157500 193500 -1.000000]
+Thermal[0.500000]
+DRC[699 400 800 399]
+Flags(0x0000000000001058)
+Groups("1,s:4,c:2:3:5,6,7,8:")
+Styles["Signal,1000,3100,1500,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,800,3600,2000,1000"]
+
+Symbol[' ' 1800]
+(
+)
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+Symbol['7' 1200]
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+	SymbolLine[0 4000 2500 4000 800]
+)
+Symbol['[' 1200]
+(
+	SymbolLine[0 0 500 0 800]
+	SymbolLine[0 0 0 4000 800]
+	SymbolLine[0 4000 500 4000 800]
+)
+Symbol['\' 1200]
+(
+	SymbolLine[0 500 3000 3500 800]
+)
+Symbol[']' 1200]
+(
+	SymbolLine[0 0 500 0 800]
+	SymbolLine[500 0 500 4000 800]
+	SymbolLine[0 4000 500 4000 800]
+)
+Symbol['^' 1200]
+(
+	SymbolLine[0 500 500 0 800]
+	SymbolLine[500 0 1000 500 800]
+)
+Symbol['_' 1200]
+(
+	SymbolLine[0 4000 2000 4000 800]
+)
+Symbol['a' 1200]
+(
+	SymbolLine[1500 2000 2000 2500 800]
+	SymbolLine[500 2000 1500 2000 800]
+	SymbolLine[0 2500 500 2000 800]
+	SymbolLine[0 2500 0 3500 800]
+	SymbolLine[0 3500 500 4000 800]
+	SymbolLine[2000 2000 2000 3500 800]
+	SymbolLine[2000 3500 2500 4000 800]
+	SymbolLine[500 4000 1500 4000 800]
+	SymbolLine[1500 4000 2000 3500 800]
+)
+Symbol['b' 1200]
+(
+	SymbolLine[0 0 0 4000 800]
+	SymbolLine[0 3500 500 4000 800]
+	SymbolLine[500 4000 1500 4000 800]
+	SymbolLine[1500 4000 2000 3500 800]
+	SymbolLine[2000 2500 2000 3500 800]
+	SymbolLine[1500 2000 2000 2500 800]
+	SymbolLine[500 2000 1500 2000 800]
+	SymbolLine[0 2500 500 2000 800]
+)
+Symbol['c' 1200]
+(
+	SymbolLine[500 2000 2000 2000 800]
+	SymbolLine[0 2500 500 2000 800]
+	SymbolLine[0 2500 0 3500 800]
+	SymbolLine[0 3500 500 4000 800]
+	SymbolLine[500 4000 2000 4000 800]
+)
+Symbol['d' 1200]
+(
+	SymbolLine[2000 0 2000 4000 800]
+	SymbolLine[1500 4000 2000 3500 800]
+	SymbolLine[500 4000 1500 4000 800]
+	SymbolLine[0 3500 500 4000 800]
+	SymbolLine[0 2500 0 3500 800]
+	SymbolLine[0 2500 500 2000 800]
+	SymbolLine[500 2000 1500 2000 800]
+	SymbolLine[1500 2000 2000 2500 800]
+)
+Symbol['e' 1200]
+(
+	SymbolLine[500 4000 2000 4000 800]
+	SymbolLine[0 3500 500 4000 800]
+	SymbolLine[0 2500 0 3500 800]
+	SymbolLine[0 2500 500 2000 800]
+	SymbolLine[500 2000 1500 2000 800]
+	SymbolLine[1500 2000 2000 2500 800]
+	SymbolLine[0 3000 2000 3000 800]
+	SymbolLine[2000 3000 2000 2500 800]
+)
+Symbol['f' 1000]
+(
+	SymbolLine[500 500 500 4000 800]
+	SymbolLine[500 500 1000 0 800]
+	SymbolLine[1000 0 1500 0 800]
+	SymbolLine[0 2000 1000 2000 800]
+)
+Symbol['g' 1200]
+(
+	SymbolLine[1500 2000 2000 2500 800]
+	SymbolLine[500 2000 1500 2000 800]
+	SymbolLine[0 2500 500 2000 800]
+	SymbolLine[0 2500 0 3500 800]
+	SymbolLine[0 3500 500 4000 800]
+	SymbolLine[500 4000 1500 4000 800]
+	SymbolLine[1500 4000 2000 3500 800]
+	SymbolLine[0 5000 500 5500 800]
+	SymbolLine[500 5500 1500 5500 800]
+	SymbolLine[1500 5500 2000 5000 800]
+	SymbolLine[2000 2000 2000 5000 800]
+)
+Symbol['h' 1200]
+(
+	SymbolLine[0 0 0 4000 800]
+	SymbolLine[0 2500 500 2000 800]
+	SymbolLine[500 2000 1500 2000 800]
+	SymbolLine[1500 2000 2000 2500 800]
+	SymbolLine[2000 2500 2000 4000 800]
+)
+Symbol['i' 1000]
+(
+	SymbolLine[0 1000 0 1500 800]
+	SymbolLine[0 2500 0 4000 800]
+)
+Symbol['j' 1000]
+(
+	SymbolLine[500 1000 500 1500 800]
+	SymbolLine[500 2500 500 5000 800]
+	SymbolLine[0 5500 500 5000 800]
+)
+Symbol['k' 1200]
+(
+	SymbolLine[0 0 0 4000 800]
+	SymbolLine[0 2500 1500 4000 800]
+	SymbolLine[0 2500 1000 1500 800]
+)
+Symbol['l' 1000]
+(
+	SymbolLine[0 0 0 3500 800]
+	SymbolLine[0 3500 500 4000 800]
+)
+Symbol['m' 1200]
+(
+	SymbolLine[500 2500 500 4000 800]
+	SymbolLine[500 2500 1000 2000 800]
+	SymbolLine[1000 2000 1500 2000 800]
+	SymbolLine[1500 2000 2000 2500 800]
+	SymbolLine[2000 2500 2000 4000 800]
+	SymbolLine[2000 2500 2500 2000 800]
+	SymbolLine[2500 2000 3000 2000 800]
+	SymbolLine[3000 2000 3500 2500 800]
+	SymbolLine[3500 2500 3500 4000 800]
+	SymbolLine[0 2000 500 2500 800]
+)
+Symbol['n' 1200]
+(
+	SymbolLine[500 2500 500 4000 800]
+	SymbolLine[500 2500 1000 2000 800]
+	SymbolLine[1000 2000 1500 2000 800]
+	SymbolLine[1500 2000 2000 2500 800]
+	SymbolLine[2000 2500 2000 4000 800]
+	SymbolLine[0 2000 500 2500 800]
+)
+Symbol['o' 1200]
+(
+	SymbolLine[0 2500 0 3500 800]
+	SymbolLine[0 2500 500 2000 800]
+	SymbolLine[500 2000 1500 2000 800]
+	SymbolLine[1500 2000 2000 2500 800]
+	SymbolLine[2000 2500 2000 3500 800]
+	SymbolLine[1500 4000 2000 3500 800]
+	SymbolLine[500 4000 1500 4000 800]
+	SymbolLine[0 3500 500 4000 800]
+)
+Symbol['p' 1200]
+(
+	SymbolLine[500 2500 500 5500 800]
+	SymbolLine[0 2000 500 2500 800]
+	SymbolLine[500 2500 1000 2000 800]
+	SymbolLine[1000 2000 2000 2000 800]
+	SymbolLine[2000 2000 2500 2500 800]
+	SymbolLine[2500 2500 2500 3500 800]
+	SymbolLine[2000 4000 2500 3500 800]
+	SymbolLine[1000 4000 2000 4000 800]
+	SymbolLine[500 3500 1000 4000 800]
+)
+Symbol['q' 1200]
+(
+	SymbolLine[2000 2500 2000 5500 800]
+	SymbolLine[1500 2000 2000 2500 800]
+	SymbolLine[500 2000 1500 2000 800]
+	SymbolLine[0 2500 500 2000 800]
+	SymbolLine[0 2500 0 3500 800]
+	SymbolLine[0 3500 500 4000 800]
+	SymbolLine[500 4000 1500 4000 800]
+	SymbolLine[1500 4000 2000 3500 800]
+)
+Symbol['r' 1200]
+(
+	SymbolLine[500 2500 500 4000 800]
+	SymbolLine[500 2500 1000 2000 800]
+	SymbolLine[1000 2000 2000 2000 800]
+	SymbolLine[0 2000 500 2500 800]
+)
+Symbol['s' 1200]
+(
+	SymbolLine[500 4000 2000 4000 800]
+	SymbolLine[2000 4000 2500 3500 800]
+	SymbolLine[2000 3000 2500 3500 800]
+	SymbolLine[500 3000 2000 3000 800]
+	SymbolLine[0 2500 500 3000 800]
+	SymbolLine[0 2500 500 2000 800]
+	SymbolLine[500 2000 2000 2000 800]
+	SymbolLine[2000 2000 2500 2500 800]
+	SymbolLine[0 3500 500 4000 800]
+)
+Symbol['t' 1000]
+(
+	SymbolLine[500 0 500 3500 800]
+	SymbolLine[500 3500 1000 4000 800]
+	SymbolLine[0 1500 1000 1500 800]
+)
+Symbol['u' 1200]
+(
+	SymbolLine[0 2000 0 3500 800]
+	SymbolLine[0 3500 500 4000 800]
+	SymbolLine[500 4000 1500 4000 800]
+	SymbolLine[1500 4000 2000 3500 800]
+	SymbolLine[2000 2000 2000 3500 800]
+)
+Symbol['v' 1200]
+(
+	SymbolLine[0 2000 0 3000 800]
+	SymbolLine[0 3000 1000 4000 800]
+	SymbolLine[1000 4000 2000 3000 800]
+	SymbolLine[2000 2000 2000 3000 800]
+)
+Symbol['w' 1200]
+(
+	SymbolLine[0 2000 0 3500 800]
+	SymbolLine[0 3500 500 4000 800]
+	SymbolLine[500 4000 1000 4000 800]
+	SymbolLine[1000 4000 1500 3500 800]
+	SymbolLine[1500 2000 1500 3500 800]
+	SymbolLine[1500 3500 2000 4000 800]
+	SymbolLine[2000 4000 2500 4000 800]
+	SymbolLine[2500 4000 3000 3500 800]
+	SymbolLine[3000 2000 3000 3500 800]
+)
+Symbol['x' 1200]
+(
+	SymbolLine[0 2000 2000 4000 800]
+	SymbolLine[0 4000 2000 2000 800]
+)
+Symbol['y' 1200]
+(
+	SymbolLine[0 2000 0 3500 800]
+	SymbolLine[0 3500 500 4000 800]
+	SymbolLine[2000 2000 2000 5000 800]
+	SymbolLine[1500 5500 2000 5000 800]
+	SymbolLine[500 5500 1500 5500 800]
+	SymbolLine[0 5000 500 5500 800]
+	SymbolLine[500 4000 1500 4000 800]
+	SymbolLine[1500 4000 2000 3500 800]
+)
+Symbol['z' 1200]
+(
+	SymbolLine[0 2000 2000 2000 800]
+	SymbolLine[0 4000 2000 2000 800]
+	SymbolLine[0 4000 2000 4000 800]
+)
+Symbol['{' 1200]
+(
+	SymbolLine[500 500 1000 0 800]
+	SymbolLine[500 500 500 1500 800]
+	SymbolLine[0 2000 500 1500 800]
+	SymbolLine[0 2000 500 2500 800]
+	SymbolLine[500 2500 500 3500 800]
+	SymbolLine[500 3500 1000 4000 800]
+)
+Symbol['|' 1200]
+(
+	SymbolLine[0 0 0 4000 800]
+)
+Symbol['}' 1200]
+(
+	SymbolLine[0 0 500 500 800]
+	SymbolLine[500 500 500 1500 800]
+	SymbolLine[500 1500 1000 2000 800]
+	SymbolLine[500 2500 1000 2000 800]
+	SymbolLine[500 2500 500 3500 800]
+	SymbolLine[0 4000 500 3500 800]
+)
+Symbol['~' 1200]
+(
+	SymbolLine[0 2500 500 2000 800]
+	SymbolLine[500 2000 1000 2000 800]
+	SymbolLine[1000 2000 1500 2500 800]
+	SymbolLine[1500 2500 2000 2500 800]
+	SymbolLine[2000 2500 2500 2000 800]
+)
+Via[70000 235000 13200 2000 11000 12800 "" 0x0800000a]
+Via[315000 235000 13200 2000 11000 12800 "" 0x0800000a]
+Via[315000 15000 13200 2000 11000 12800 "" 0x0800000a]
+Via[213000 120500 4500 1600 0 2000 "" 0x08000002]
+Via[232500 79500 6000 2000 0 2800 "" 0x08080002]
+Via[217000 83000 4500 1600 0 2000 "" 0x08000002]
+Via[221000 127500 4500 1600 0 2000 "" 0x08000002]
+Via[213000 74500 4500 1600 0 2000 "" 0x08000002]
+Via[79500 191000 6000 2000 0 3500 "" 0x08080002]
+Via[222000 72500 6000 2000 0 3500 "" 0x08080002]
+Via[101500 231000 4000 2000 0 2000 "" 0x08080002]
+Via[248500 83000 4000 2000 0 2000 "" 0x08080002]
+Via[279000 92500 6000 2000 0 3500 "" 0x08080002]
+Via[262500 156500 4000 2000 0 2000 "" 0x08080002]
+Via[241500 167500 4000 2000 0 2000 "" 0x08080002]
+Via[191000 164500 4000 2000 0 2000 "" 0x08080002]
+Via[208500 135000 4000 2000 0 2000 "" 0x08080002]
+Via[141500 91000 6000 2000 0 3500 "" 0x08080002]
+Via[160000 133000 6000 2000 0 3500 "" 0x08080002]
+Via[187500 153500 4000 2000 0 2000 "" 0x08080002]
+Via[288500 188500 6000 2000 0 3500 "" 0x08080002]
+Via[136541 161000 6000 2000 0 3500 "" 0x08000002]
+Via[227500 145000 4000 2000 0 2000 "" 0x08000002]
+Via[173000 129000 4000 2000 0 2000 "" 0x08000002]
+Via[194500 135000 4000 2000 0 2000 "" 0x08000002]
+Via[176000 228500 4000 2000 0 2000 "" 0x08000002]
+Via[197000 220500 4000 2000 0 2000 "" 0x08000002]
+Via[148000 233000 6000 2000 0 2800 "" 0x08000002]
+Via[139500 151000 6000 2000 0 2800 "" 0x08000002]
+Via[145000 169500 6000 2000 0 3500 "" 0x08000002]
+Via[172500 187500 6000 2000 0 3500 "" 0x08080002]
+Via[79500 82500 3600 2000 0 2000 "" 0x09000002]
+Via[57000 163500 3600 2000 0 2000 "" 0x09090002]
+Via[57000 145500 3600 2000 0 2000 "" 0x09090002]
+Via[57000 127500 3600 2000 0 2000 "" 0x09090002]
+Via[56500 109500 3600 2000 0 2000 "" 0x09090002]
+Via[57000 96500 3600 2000 0 2000 "" 0x09090002]
+Via[56500 76000 3600 2000 0 2000 "" 0x09090002]
+Via[72500 75000 3600 2000 0 2000 "" 0x09090002]
+Via[87000 74500 3600 2000 0 2000 "" 0x09090002]
+Via[104000 72500 3600 2000 0 2000 "" 0x09090002]
+Via[100500 105000 3600 2000 0 2000 "" 0x09090002]
+Via[57000 58000 3600 2000 0 2000 "" 0x09000002]
+Via[63000 47500 3600 2000 0 2000 "" 0x09000002]
+Via[238500 177000 6000 2000 0 3500 "" 0x08000002]
+
+Element[0x00000080 "0603" "R6" "1.6K" 104000 219000 -3000 10000 0 100 0x00000080]
+(
+	Pad[-900 -2400 900 -2400 2400 3000 2400 "1" "1" 0x00000180]
+	Pad[-900 2400 900 2400 2400 3000 2400 "2" "2" 0x00000180]
+	ElementLine [-2700 -4200 -2700 4200 600]
+	ElementLine [-2700 4200 2700 4200 600]
+	ElementLine [2700 -4200 2700 4200 600]
+	ElementLine [-2700 -4200 2700 -4200 600]
+
+	)
+
+Element[0x00000080 "0603" "R9" "10K" 203400 150500 -11400 1800 0 100 0x00000080]
+(
+	Pad[2400 -900 2400 900 2400 2000 3000 "1" "1" 0x00000180]
+	Pad[-2400 -900 -2400 900 2400 2000 3000 "2" "2" 0x00000180]
+	ElementLine [-4200 -2700 4200 -2700 600]
+	ElementLine [-4200 -2700 -4200 2700 600]
+	ElementLine [-4200 2700 4200 2700 600]
+	ElementLine [4200 -2700 4200 2700 600]
+
+	)
+
+Element[0x00000080 "0603" "R10" "0" 270500 69500 -2000 -15500 1 100 0x00000080]
+(
+	Pad[-900 -2400 900 -2400 2400 3000 2400 "1" "1" 0x00000180]
+	Pad[-900 2400 900 2400 2400 3000 2400 "2" "2" 0x00000180]
+	ElementLine [-2700 -4200 -2700 4200 600]
+	ElementLine [-2700 4200 2700 4200 600]
+	ElementLine [2700 -4200 2700 4200 600]
+	ElementLine [-2700 -4200 2700 -4200 600]
+
+	)
+
+Element[0x00000080 "0603" "R17" "0" 263500 69000 -2200 -15500 1 100 0x00000080]
+(
+	Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" 0x00000180]
+	Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" 0x00000180]
+	ElementLine [-2700 -4200 -2700 4200 600]
+	ElementLine [-2700 4200 2700 4200 600]
+	ElementLine [2700 -4200 2700 4200 600]
+	ElementLine [-2700 -4200 2700 -4200 600]
+
+	)
+
+Element[0x00000080 "0603" "C3" ".1uF" 254500 158500 7500 2700 0 100 0x00000080]
+(
+	Pad[2400 -900 2400 900 2400 2000 3000 "1" "1" 0x00000180]
+	Pad[-2400 -900 -2400 900 2400 2000 3000 "2" "2" 0x00000180]
+	ElementLine [-4200 -2700 4200 -2700 600]
+	ElementLine [-4200 -2700 -4200 2700 600]
+	ElementLine [-4200 2700 4200 2700 600]
+	ElementLine [4200 -2700 4200 2700 600]
+
+	)
+
+Element[0x00000000 "MT4937DI5" "U2" "unknown" 312500 202000 -8000 13500 0 100 0x00000000]
+(
+	Pin[-297800 -700 7500 2000 8100 5000 "" "18" 0x08004001]
+	Pin[-280300 -700 7500 2000 8100 5000 "" "17" 0x08004001]
+	Pin[-262800 -700 7500 2000 8100 5000 "" "16" 0x08004001]
+	Pin[-245300 -700 7500 2000 8100 5000 "" "15" 0x08004001]
+	Pin[-227800 -700 7500 2000 8100 5000 "" "14" 0x08004001]
+	Pin[-210300 -700 7500 2000 8100 5000 "" "13" 0x08004001]
+	Pin[-192800 -700 7500 2000 8100 5000 "" "12" 0x08004001]
+	Pin[-175300 -700 7500 2000 8100 5000 "" "11" 0x08004001]
+	Pin[-157800 -700 7500 2000 8100 5000 "" "10" 0x08004001]
+	Pin[-140300 -700 7500 2000 8100 5000 "" "9" 0x08004001]
+	Pin[-122800 -700 7500 2000 8100 5000 "" "8" 0x08004001]
+	Pin[-105300 -700 7500 2000 8100 5000 "" "7" 0x08004001]
+	Pin[-87800 -700 7500 2000 8100 5000 "" "6" 0x08004001]
+	Pin[-70300 -700 7500 2000 8100 5000 "" "5" 0x08084001]
+	Pin[-52800 -700 7500 2000 8100 5000 "" "4" 0x08004001]
+	Pin[-35300 -700 7500 2000 8100 5000 "" "3" 0x08004001]
+	Pin[-17800 -700 7500 2000 8100 5000 "" "2" 0x08004001]
+	Pin[-300 -700 7500 2000 8100 5000 "" "1" 0x08004001]
+	Pin[-303400 -10900 14000 2000 14600 11000 "" "21" 0x08004001]
+	Pin[-303400 -147500 21000 2000 21600 11000 "" "22" 0x08084001]
+	Pin[5300 -147500 21000 2000 21600 11000 "" "23" 0x08084001]
+	Pin[5300 -10900 14000 2000 14600 11000 "" "24" 0x08004001]
+	ElementLine [-312200 9000 -312200 11400 1500]
+	ElementLine [-311600 11300 14400 11300 1500]
+	ElementLine [14400 -156600 14400 11300 1500]
+	ElementLine [14700 -156900 14400 -156600 1500]
+	ElementLine [14400 -157200 14700 -156900 1500]
+	ElementLine [-312200 -157200 14400 -157200 1500]
+	ElementLine [-312200 -157200 -312200 9200 1500]
+
+	)
+
+Element[0x00000080 "SO8" "U1" "unknown" 187500 128500 -3000 -4000 0 100 0x00000080]
+(
+	Pad[-900 0 1900 0 2000 3000 2000 "1" "1" 0x00004080]
+	Pad[-900 5000 1900 5000 2000 3000 2000 "2" "2" 0x00004180]
+	Pad[-900 10000 1900 10000 2000 3000 2000 "3" "3" 0x00004180]
+	Pad[-900 15000 1900 15000 2000 3000 2000 "4" "4" 0x00004180]
+	Pad[-21300 15000 -18500 15000 2000 3000 2000 "5" "5" 0x00000180]
+	Pad[-21300 10000 -18500 10000 2000 3000 2000 "6" "6" 0x00000180]
+	Pad[-21300 5000 -18500 5000 2000 3000 2000 "7" "7" 0x00000180]
+	Pad[-21300 0 -18500 0 2000 3000 2000 "8" "8" 0x00000180]
+	ElementLine [2900 17500 2900 -2500 1000]
+	ElementLine [-22300 17500 2900 17500 1000]
+	ElementLine [-22300 17500 -22300 -2500 1000]
+	ElementLine [-22300 -2500 -7200 -2500 1000]
+	ElementLine [-12200 -2500 2900 -2500 1000]
+	ElementArc [-9700 -2500 2500 2500 0 180 1000]
+
+	)
+
+Element[0x00000080 "0603" "C1" ".1uF" 270500 79000 5000 -2300 0 100 0x00000080]
+(
+	Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" 0x00000180]
+	Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" 0x00000180]
+	ElementLine [2700 -4200 2700 4200 600]
+	ElementLine [-2700 -4200 2700 -4200 600]
+	ElementLine [-2700 -4200 -2700 4200 600]
+	ElementLine [-2700 4200 2700 4200 600]
+
+	)
+
+Element[0x00000000 "CONNECTOR-8-2" "J24" "unknown" 184500 23500 -16200 -7100 0 100 0x00000000]
+(
+	Pin[0 0 6000 3000 6600 4000 "1" "1" 0x08004101]
+	Pin[0 -10000 6000 3000 6600 4000 "2" "2" 0x080a4001]
+	Pin[10000 0 6000 3000 6600 4000 "3" "3" 0x08004001]
+	Pin[10000 -10000 6000 3000 6600 4000 "4" "4" 0x080a4001]
+	Pin[20000 0 6000 3000 6600 4000 "5" "5" 0x08004001]
+	Pin[20000 -10000 6000 3000 6600 4000 "6" "6" 0x080a4001]
+	Pin[30000 0 6000 3000 6600 4000 "7" "7" 0x08004001]
+	Pin[30000 -10000 6000 3000 6600 4000 "8" "8" 0x080a4001]
+	Pin[40000 0 6000 3000 6600 4000 "9" "9" 0x08004001]
+	Pin[40000 -10000 6000 3000 6600 4000 "10" "10" 0x080a4001]
+	Pin[50000 0 6000 3000 6600 4000 "11" "11" 0x08004001]
+	Pin[50000 -10000 6000 3000 6600 4000 "12" "12" 0x080a4001]
+	Pin[60000 0 6000 3000 6600 4000 "13" "13" 0x08004001]
+	Pin[60000 -10000 6000 3000 6600 4000 "14" "14" 0x080a4001]
+	Pin[70000 0 6000 3000 6600 4000 "15" "15" 0x08004001]
+	Pin[70000 -10000 6000 3000 6600 4000 "16" "16" 0x080a4001]
+	ElementLine [-5000 -5000 5000 -5000 1000]
+	ElementLine [5000 -5000 5000 5000 1000]
+	ElementLine [-5000 -15000 -5000 5000 2000]
+	ElementLine [-5000 -15000 75000 -15000 2000]
+	ElementLine [75000 -15000 75000 5000 2000]
+	ElementLine [-5000 5000 75000 5000 2000]
+
+	)
+
+Element[0x00000080 "0603" "C2" ".1uF" 263500 79000 -10500 -3300 0 100 0x00000080]
+(
+	Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" 0x00000180]
+	Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" 0x00000180]
+	ElementLine [2700 -4200 2700 4200 600]
+	ElementLine [-2700 -4200 2700 -4200 600]
+	ElementLine [-2700 -4200 -2700 4200 600]
+	ElementLine [-2700 4200 2700 4200 600]
+
+	)
+
+Element[0x00000080 "0603" "R4" "2.2K" 140500 219500 -3500 9700 0 100 0x00000080]
+(
+	Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" 0x00000180]
+	Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" 0x00000180]
+	ElementLine [2700 -4200 2700 4200 600]
+	ElementLine [-2700 -4200 2700 -4200 600]
+	ElementLine [-2700 -4200 -2700 4200 600]
+	ElementLine [-2700 4200 2700 4200 600]
+
+	)
+
+Element[0x00000080 "SOT23" "Q1" "unknown" 163000 228500 -6000 8800 0 100 0x00000080]
+(
+	Pad[0 -300 0 300 3400 3000 4000 "1" "1" 0x00004180]
+	Pad[-7800 -300 -7800 300 3400 3000 4000 "2" "2" 0x00004180]
+	Pad[-3900 -8500 -3900 -7900 3400 3000 4000 "3" "3" 0x00000180]
+	ElementLine [-10300 -11000 2500 -11000 1000]
+	ElementLine [-10300 2900 -10300 -11000 1000]
+	ElementLine [-10300 2900 2500 2900 1000]
+	ElementLine [2500 2900 2500 -11000 1000]
+
+	)
+
+Element[0x00000080 "0603" "R1" "NONE" 148000 224500 -3000 9700 0 100 0x00000080]
+(
+	Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" 0x00000180]
+	Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" 0x00000180]
+	ElementLine [2700 -4200 2700 4200 600]
+	ElementLine [-2700 -4200 2700 -4200 600]
+	ElementLine [-2700 -4200 -2700 4200 600]
+	ElementLine [-2700 4200 2700 4200 600]
+
+	)
+
+Element[0x00000080 "0603" "R2" "2.2K" 171000 218000 -4000 9700 0 100 0x00000080]
+(
+	Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" 0x00000180]
+	Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" 0x00000180]
+	ElementLine [2700 -4200 2700 4200 600]
+	ElementLine [-2700 -4200 2700 -4200 600]
+	ElementLine [-2700 -4200 -2700 4200 600]
+	ElementLine [-2700 4200 2700 4200 600]
+
+	)
+
+Element[0x00000080 "0603" "C5" "10pF" 279000 82000 6000 2200 0 100 0x00000080]
+(
+	Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" 0x00000180]
+	Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" 0x00000180]
+	ElementLine [4200 2700 -4200 2700 600]
+	ElementLine [4200 -2700 4200 2700 600]
+	ElementLine [-4200 -2700 4200 -2700 600]
+	ElementLine [-4200 2700 -4200 -2700 600]
+
+	)
+
+Element[0x00000080 "0603" "C6" "10pF" 255000 82000 -12000 2200 0 100 0x00000080]
+(
+	Pad[2400 -900 2400 900 2400 2000 3000 "1" "1" 0x00000180]
+	Pad[-2400 -900 -2400 900 2400 2000 3000 "2" "2" 0x00000180]
+	ElementLine [-4200 -2700 4200 -2700 600]
+	ElementLine [-4200 -2700 -4200 2700 600]
+	ElementLine [-4200 2700 4200 2700 600]
+	ElementLine [4200 -2700 4200 2700 600]
+
+	)
+
+Element[0x00000000 "CONNECTOR-8-2" "J25" "unknown" 89000 24000 -15800 -5600 0 100 0x00000000]
+(
+	Pin[0 0 6000 3000 6600 4000 "1" "1" 0x08004101]
+	Pin[0 -10000 6000 3000 6600 4000 "2" "2" 0x080a4001]
+	Pin[10000 0 6000 3000 6600 4000 "3" "3" 0x08004001]
+	Pin[10000 -10000 6000 3000 6600 4000 "4" "4" 0x080a4001]
+	Pin[20000 0 6000 3000 6600 4000 "5" "5" 0x08004001]
+	Pin[20000 -10000 6000 3000 6600 4000 "6" "6" 0x080a4001]
+	Pin[30000 0 6000 3000 6600 4000 "7" "7" 0x08004001]
+	Pin[30000 -10000 6000 3000 6600 4000 "8" "8" 0x080a4001]
+	Pin[40000 0 6000 3000 6600 4000 "9" "9" 0x08004001]
+	Pin[40000 -10000 6000 3000 6600 4000 "10" "10" 0x080a4001]
+	Pin[50000 0 6000 3000 6600 4000 "11" "11" 0x08004001]
+	Pin[50000 -10000 6000 3000 6600 4000 "12" "12" 0x080a4001]
+	Pin[60000 0 6000 3000 6600 4000 "13" "13" 0x08004001]
+	Pin[60000 -10000 6000 3000 6600 4000 "14" "14" 0x080a4001]
+	Pin[70000 0 6000 3000 6600 4000 "15" "15" 0x08004001]
+	Pin[70000 -10000 6000 3000 6600 4000 "16" "16" 0x080a4001]
+	ElementLine [-5000 -5000 5000 -5000 1000]
+	ElementLine [5000 -5000 5000 5000 1000]
+	ElementLine [-5000 -15000 -5000 5000 2000]
+	ElementLine [-5000 -15000 75000 -15000 2000]
+	ElementLine [75000 -15000 75000 5000 2000]
+	ElementLine [-5000 5000 75000 5000 2000]
+
+	)
+
+Element[0x00000080 "PMC-REVERSE" "J2" "unknown" 149993 95811 -18000 9000 0 100 0x00000080]
+(
+	Pin[-6693 7189 7200 2000 7200 5800 "" "1" 0x08004009]
+	Pin[128740 7189 7200 2000 7200 5800 "" "2" 0x08004009]
+	Pad[0 9900 0 19000 2400 1000 3400 "" "1" 0x00004080]
+	Pad[122047 -4622 122047 4478 2400 1000 3400 "" "64" 0x00000080]
+	Pad[7874 9900 7874 19000 2400 1000 3400 "" "5" 0x00004080]
+	Pad[3937 9900 3937 19000 2400 1000 3400 "" "3" 0x00004080]
+	Pad[11811 9900 11811 19000 2400 1000 3400 "" "7" 0x00004080]
+	Pad[0 -4622 0 4478 2400 1000 3400 "" "2" 0x00000080]
+	Pad[15748 9900 15748 19000 2400 1000 3400 "" "9" 0x00004080]
+	Pad[7874 -4622 7874 4478 2400 1000 3400 "" "6" 0x00000080]
+	Pad[19685 9900 19685 19000 2400 1000 3400 "" "11" 0x00004080]
+	Pad[11811 -4622 11811 4478 2400 1000 3400 "" "8" 0x00000080]
+	Pad[23622 9900 23622 19000 2400 1000 3400 "" "13" 0x00004080]
+	Pad[15748 -4622 15748 4478 2400 1000 3400 "" "10" 0x00000080]
+	Pad[27559 9900 27559 19000 2400 1000 3400 "" "15" 0x00004080]
+	Pad[19685 -4622 19685 4478 2400 1000 3400 "" "12" 0x00000080]
+	Pad[31496 9900 31496 19000 2400 1000 3400 "" "17" 0x00004080]
+	Pad[23622 -4622 23622 4478 2400 1000 3400 "" "14" 0x00000080]
+	Pad[35433 9900 35433 19000 2400 1000 3400 "" "19" 0x00004080]
+	Pad[27559 -4622 27559 4478 2400 1000 3400 "" "16" 0x00000080]
+	Pad[39370 9900 39370 19000 2400 1000 3400 "" "21" 0x00004080]
+	Pad[31496 -4622 31496 4478 2400 1000 3400 "" "18" 0x00000080]
+	Pad[35433 -4622 35433 4478 2400 1000 3400 "" "20" 0x00000080]
+	Pad[39370 -4622 39370 4478 2400 1000 3400 "" "22" 0x00000080]
+	Pad[43307 -4622 43307 4478 2400 1000 3400 "" "24" 0x00000080]
+	Pad[47244 -4622 47244 4478 2400 1000 3400 "" "26" 0x00000080]
+	Pad[51181 -4622 51181 4478 2400 1000 3400 "" "28" 0x00000080]
+	Pad[55118 -4622 55118 4478 2400 1000 3400 "" "30" 0x00000080]
+	Pad[59055 -4622 59055 4478 2400 1000 3400 "" "32" 0x00000080]
+	Pad[62992 -4622 62992 4478 2400 1000 3400 "" "34" 0x00000080]
+	Pad[66929 -4622 66929 4478 2400 1000 3400 "" "36" 0x00000080]
+	Pad[70866 -4622 70866 4478 2400 1000 3400 "" "38" 0x00000080]
+	Pad[74803 -4622 74803 4478 2400 1000 3400 "" "40" 0x00000080]
+	Pad[78740 -4622 78740 4478 2400 1000 3400 "" "42" 0x00000080]
+	Pad[82677 -4622 82677 4478 2400 1000 3400 "" "44" 0x00000080]
+	Pad[86614 -4622 86614 4478 2400 1000 3400 "" "46" 0x00000080]
+	Pad[90551 -4622 90551 4478 2400 1000 3400 "" "48" 0x00000080]
+	Pad[98425 -4622 98425 4478 2400 1000 3400 "" "52" 0x00000080]
+	Pad[94488 -4622 94488 4478 2400 1000 3400 "" "50" 0x00000080]
+	Pad[102362 -4622 102362 4478 2400 1000 3400 "" "54" 0x00000080]
+	Pad[106299 -4622 106299 4478 2400 1000 3400 "" "56" 0x00000080]
+	Pad[110236 -4622 110236 4478 2400 1000 3400 "" "58" 0x00000080]
+	Pad[114173 -4622 114173 4478 2400 1000 3400 "" "60" 0x00000080]
+	Pad[3937 -4622 3937 4478 2400 1000 3400 "" "4" 0x00000080]
+	Pad[43307 9900 43307 19000 2400 1000 3400 "" "23" 0x00004080]
+	Pad[47244 9900 47244 19000 2400 1000 3400 "" "25" 0x00004080]
+	Pad[51181 9900 51181 19000 2400 1000 3400 "" "27" 0x00004080]
+	Pad[55118 9900 55118 19000 2400 1000 3400 "" "29" 0x00004080]
+	Pad[59055 9900 59055 19000 2400 1000 3400 "" "31" 0x00004080]
+	Pad[62992 9900 62992 19000 2400 1000 3400 "" "33" 0x00004080]
+	Pad[66929 9900 66929 19000 2400 1000 3400 "" "35" 0x00004080]
+	Pad[70866 9900 70866 19000 2400 1000 3400 "" "37" 0x00004080]
+	Pad[74803 9900 74803 19000 2400 1000 3400 "" "39" 0x00004080]
+	Pad[78740 9900 78740 19000 2400 1000 3400 "" "41" 0x00004080]
+	Pad[82677 9900 82677 19000 2400 1000 3400 "" "43" 0x00004080]
+	Pad[86614 9900 86614 19000 2400 1000 3400 "" "45" 0x00004080]
+	Pad[90551 9900 90551 19000 2400 1000 3400 "" "47" 0x00004080]
+	Pad[94488 9900 94488 19000 2400 1000 3400 "" "49" 0x00004080]
+	Pad[98425 9900 98425 19000 2400 1000 3400 "" "51" 0x00004080]
+	Pad[102362 9900 102362 19000 2400 1000 3400 "" "53" 0x00004080]
+	Pad[106299 9900 106299 19000 2400 1000 3400 "" "55" 0x00004080]
+	Pad[110236 9900 110236 19000 2400 1000 3400 "" "57" 0x00004080]
+	Pad[114173 9900 114173 19000 2400 1000 3400 "" "59" 0x00004080]
+	Pad[118110 9900 118110 19000 2400 1000 3400 "" "61" 0x00004080]
+	Pad[122047 9900 122047 19000 2400 1000 3400 "" "63" 0x00004080]
+	Pad[118110 -4622 118110 4478 2400 1000 3400 "" "62" 0x00000080]
+	ElementLine [134000 -9000 134000 24000 1000]
+	ElementLine [-11000 24000 134000 24000 1000]
+	ElementLine [-11000 -9000 134000 -9000 1000]
+	ElementLine [-11000 -9000 -11000 24000 1000]
+
+	)
+
+Element[0x00000080 "0603" "R7" "10K" 252000 147500 6000 -2000 0 100 0x00000080]
+(
+	Pad[-900 -2400 900 -2400 2400 3000 2400 "1" "1" 0x00000180]
+	Pad[-900 2400 900 2400 2400 3000 2400 "2" "2" 0x00000180]
+	ElementLine [-2700 4200 -2700 -4200 600]
+	ElementLine [-2700 4200 2700 4200 600]
+	ElementLine [2700 4200 2700 -4200 600]
+	ElementLine [-2700 -4200 2700 -4200 600]
+
+	)
+
+Element[0x00000080 "0603" "R11" "NONE" 221000 135500 4000 2200 0 100 0x00000080]
+(
+	Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" 0x00000180]
+	Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" 0x00000180]
+	ElementLine [2700 -4200 2700 4200 600]
+	ElementLine [-2700 -4200 2700 -4200 600]
+	ElementLine [-2700 -4200 -2700 4200 600]
+	ElementLine [-2700 4200 2700 4200 600]
+
+	)
+
+Element[0x00000080 "0603" "R12" "10K" 243500 133000 6000 2200 0 100 0x00000080]
+(
+	Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" 0x00000180]
+	Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" 0x00000180]
+	ElementLine [2700 -4200 2700 4200 600]
+	ElementLine [-2700 -4200 2700 -4200 600]
+	ElementLine [-2700 -4200 -2700 4200 600]
+	ElementLine [-2700 4200 2700 4200 600]
+
+	)
+
+Element[0x00000080 "0603" "C4" ".1uF" 202500 162500 -3500 8200 0 100 0x00000080]
+(
+	Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" 0x00000180]
+	Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" 0x00000180]
+	ElementLine [-4200 2700 4200 2700 600]
+	ElementLine [4200 -2700 4200 2700 600]
+	ElementLine [-4200 -2700 4200 -2700 600]
+	ElementLine [-4200 -2700 -4200 2700 600]
+
+	)
+
+Element[0x00000080 "0603" "R16" "10K" 201000 141500 5000 700 0 100 0x00000080]
+(
+	Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" 0x00000180]
+	Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" 0x00000180]
+	ElementLine [2700 -4200 2700 4200 600]
+	ElementLine [-2700 -4200 2700 -4200 600]
+	ElementLine [-2700 -4200 -2700 4200 600]
+	ElementLine [-2700 4200 2700 4200 600]
+
+	)
+
+Element[0x00000080 "0603" "R13" "NONE" 209500 127000 -12500 700 0 100 0x00000080]
+(
+	Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" 0x00000180]
+	Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" 0x00000180]
+	ElementLine [2700 -4200 2700 4200 600]
+	ElementLine [-2700 -4200 2700 -4200 600]
+	ElementLine [-2700 -4200 -2700 4200 600]
+	ElementLine [-2700 4200 2700 4200 600]
+
+	)
+
+Element[0x00000080 "SO8" "U4" "unknown" 228000 153000 -3500 16000 0 100 0x00000080]
+(
+	Pad[7000 -7500 13500 -7500 2000 1000 3000 "1" "1" 0x00004180]
+	Pad[7000 -2500 13500 -2500 2000 1000 3000 "2" "2" 0x00004180]
+	Pad[7000 2500 13500 2500 2000 1000 3000 "3" "3" 0x00004180]
+	Pad[7000 7500 13500 7500 2000 1000 3000 "4" "4" 0x00004180]
+	Pad[-13500 7500 -7000 7500 2000 1000 3000 "5" "5" 0x00000180]
+	Pad[-13500 2500 -7000 2500 2000 1000 3000 "6" "6" 0x00000180]
+	Pad[-13500 -2500 -7000 -2500 2000 1000 3000 "7" "7" 0x00000180]
+	Pad[-13500 -7500 -7000 -7500 2000 1000 3000 "8" "8" 0x00000180]
+	ElementLine [-15500 -9500 -2500 -9500 1000]
+	ElementLine [2500 -9500 15500 -9500 1000]
+	ElementLine [-15500 -9500 -15500 9500 1000]
+	ElementLine [-15500 9500 15500 9500 1000]
+	ElementLine [15500 -9500 15500 9500 1000]
+	ElementArc [0 -9500 2500 2500 0 180 1000]
+
+	)
+
+Element[0x00000080 "0603" "R14" "10K" 244500 124500 6500 2200 0 100 0x00000080]
+(
+	Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" 0x00000180]
+	Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" 0x00000180]
+	ElementLine [-4200 2700 4200 2700 600]
+	ElementLine [4200 -2700 4200 2700 600]
+	ElementLine [-4200 -2700 4200 -2700 600]
+	ElementLine [-4200 -2700 -4200 2700 600]
+
+	)
+
+Element[0x00000080 "0603" "R8" "10K" 263000 150500 6000 2200 0 100 0x00000080]
+(
+	Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" 0x00000180]
+	Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" 0x00000180]
+	ElementLine [4200 2700 -4200 2700 600]
+	ElementLine [4200 -2700 4200 2700 600]
+	ElementLine [-4200 -2700 4200 -2700 600]
+	ElementLine [-4200 2700 -4200 -2700 600]
+
+	)
+
+Element[0x00000080 "SOT23" "Q2" "unknown" 132000 230000 -7000 8300 0 100 0x00000080]
+(
+	Pad[0 -300 0 300 3400 3000 4000 "1" "1" 0x00004180]
+	Pad[-7800 -300 -7800 300 3400 3000 4000 "2" "2" 0x00004180]
+	Pad[-3900 -8500 -3900 -7900 3400 3000 4000 "3" "3" 0x00000180]
+	ElementLine [-10300 -11000 2500 -11000 1000]
+	ElementLine [-10300 -11000 -10300 2900 1000]
+	ElementLine [-10300 2900 2500 2900 1000]
+	ElementLine [2500 -11000 2500 2900 1000]
+
+	)
+
+Element[0x00000080 "0603" "R3" "NONE" 116500 225500 -4500 9700 0 100 0x00000080]
+(
+	Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" 0x00000180]
+	Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" 0x00000180]
+	ElementLine [2700 -4200 2700 4200 600]
+	ElementLine [-2700 -4200 2700 -4200 600]
+	ElementLine [-2700 -4200 -2700 4200 600]
+	ElementLine [-2700 4200 2700 4200 600]
+
+	)
+
+Element[0x00000080 "0603" "R5" "1K" 96000 219000 -4000 10000 0 100 0x00000080]
+(
+	Pad[-900 2400 900 2400 2400 3000 2400 "1" "1" 0x00000180]
+	Pad[-900 -2400 900 -2400 2400 3000 2400 "2" "2" 0x00000180]
+	ElementLine [2700 -4200 2700 4200 600]
+	ElementLine [-2700 -4200 2700 -4200 600]
+	ElementLine [-2700 -4200 -2700 4200 600]
+	ElementLine [-2700 4200 2700 4200 600]
+
+	)
+
+Element[0x00000080 "SOT223" "U3" "unknown" 116800 117400 -5300 14600 0 100 0x00000080]
+(
+	Pad[0 -3300 0 3300 5600 3000 6200 "1" "1" 0x00004180]
+	Pad[-9000 -3300 -9000 3300 5600 3000 6200 "2" "2" 0x00004180]
+	Pad[-18100 -3300 -18100 3300 5600 3000 6200 "3" "3" 0x00004180]
+	Pad[-13500 -24400 -4500 -24400 12200 3000 12800 "4" "4" 0x00004180]
+	ElementLine [-23300 -32900 5200 -32900 1000]
+	ElementLine [-23300 -32900 -23300 8500 1000]
+	ElementLine [-23300 8500 5200 8500 1000]
+	ElementLine [5200 -32900 5200 8500 1000]
+
+	)
+
+Element[0x00000080 "EIA6032" "C82" "22uF" 76000 104000 -6000 24800 0 100 0x00000080]
+(
+	Pad[-3900 9400 3900 9400 9700 2000 10300 "1" "1" 0x00000180]
+	Pad[-3900 -9400 3900 -9400 9700 2000 10300 "2" "2" 0x00000180]
+	ElementLine [11200 13000 8700 17800 1000]
+	ElementLine [11200 -16800 11200 13000 1000]
+	ElementLine [-11200 -16800 11200 -16800 1000]
+	ElementLine [-11200 -16800 -11200 13000 1000]
+	ElementLine [-8700 17800 -11200 13000 1000]
+	ElementLine [-8700 17800 8700 17800 2000]
+
+	)
+
+Element[0x00000080 "0603" "C83" ".1uF" 127500 105500 -2000 10700 0 100 0x00000080]
+(
+	Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" 0x00000180]
+	Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" 0x00000180]
+	ElementLine [-2700 -4200 -2700 4200 600]
+	ElementLine [-2700 4200 2700 4200 600]
+	ElementLine [2700 -4200 2700 4200 600]
+	ElementLine [-2700 -4200 2700 -4200 600]
+
+	)
+
+Element[0x00000080 "1206" "C102" "4.7uF" 281500 179000 10000 2400 0 100 0x00000080]
+(
+	Pad[-4800 -1800 -4800 1800 4800 2000 5400 "1" "1" 0x00000180]
+	Pad[4800 -1800 4800 1800 4800 2000 5400 "2" "2" 0x00000180]
+	ElementLine [-8400 5400 8400 5400 1000]
+	ElementLine [8400 -5400 8400 5400 1000]
+	ElementLine [-8400 -5400 8400 -5400 1000]
+	ElementLine [-8400 -5400 -8400 5400 1000]
+
+	)
+
+Element[0x00000080 "0603" "C101" "470pF" 279500 189500 6000 1700 0 100 0x00000080]
+(
+	Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" 0x00000180]
+	Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" 0x00000180]
+	ElementLine [-4200 2700 4200 2700 600]
+	ElementLine [4200 -2700 4200 2700 600]
+	ElementLine [-4200 -2700 4200 -2700 600]
+	ElementLine [-4200 -2700 -4200 2700 600]
+
+	)
+
+Element[0x00000080 "1206" "C104" "4.7uF" 234000 216500 11000 1900 0 100 0x00000080]
+(
+	Pad[-4800 -1800 -4800 1800 4800 2000 5400 "1" "1" 0x00000180]
+	Pad[4800 -1800 4800 1800 4800 2000 5400 "2" "2" 0x00000180]
+	ElementLine [8400 5400 -8400 5400 1000]
+	ElementLine [8400 -5400 8400 5400 1000]
+	ElementLine [-8400 -5400 8400 -5400 1000]
+	ElementLine [-8400 5400 -8400 -5400 1000]
+
+	)
+
+Element[0x00000080 "0603" "C103" "470pF" 233000 192500 6200 0 3 100 0x00000080]
+(
+	Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" 0x00000180]
+	Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" 0x00000180]
+	ElementLine [4200 2700 -4200 2700 600]
+	ElementLine [4200 -2700 4200 2700 600]
+	ElementLine [-4200 -2700 4200 -2700 600]
+	ElementLine [-4200 2700 -4200 -2700 600]
+
+	)
+
+Element[0x00000080 "1206" "C106" "4.7uF" 159500 184000 10000 2900 0 100 0x00000080]
+(
+	Pad[-4800 -1800 -4800 1800 4800 2000 5400 "1" "1" 0x00000180]
+	Pad[4800 -1800 4800 1800 4800 2000 5400 "2" "2" 0x00000180]
+	ElementLine [8400 5400 -8400 5400 1000]
+	ElementLine [8400 -5400 8400 5400 1000]
+	ElementLine [-8400 -5400 8400 -5400 1000]
+	ElementLine [-8400 5400 -8400 -5400 1000]
+
+	)
+
+Element[0x000000c0 "0603" "C105" "470pF" 157500 193500 5500 1200 0 100 0x00000080]
+(
+	Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" 0x00000180]
+	Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" 0x00000180]
+	ElementLine [4200 2700 -4200 2700 600]
+	ElementLine [4200 -2700 4200 2700 600]
+	ElementLine [-4200 -2700 4200 -2700 600]
+	ElementLine [-4200 2700 -4200 -2700 600]
+
+	)
+
+Element[0x00000080 "1206" "C108" "4.7uF" 74000 180500 -22500 1400 0 100 0x00000080]
+(
+	Pad[-4800 -1800 -4800 1800 4800 2000 5400 "1" "1" 0x00000180]
+	Pad[4800 -1800 4800 1800 4800 2000 5400 "2" "2" 0x00000180]
+	ElementLine [8400 5400 -8400 5400 1000]
+	ElementLine [8400 -5400 8400 5400 1000]
+	ElementLine [-8400 -5400 8400 -5400 1000]
+	ElementLine [-8400 5400 -8400 -5400 1000]
+
+	)
+
+Element[0x000000c0 "0603" "C107" "470pF" 70500 190500 -18500 1700 0 100 0x00000080]
+(
+	Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" 0x00000180]
+	Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" 0x00000180]
+	ElementLine [4200 2700 -4200 2700 600]
+	ElementLine [4200 -2700 4200 2700 600]
+	ElementLine [-4200 -2700 4200 -2700 600]
+	ElementLine [-4200 2700 -4200 -2700 600]
+
+	)
+Layer(1 "solder")
+(
+	Line[209000 49000 209000 93000 1000 2000 0x00000000]
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+	Line[177000 62000 177000 93000 1000 2000 0x00000000]
+	Line[149000 24000 182000 57000 1000 2000 0x00000000]
+	Line[182000 57000 182000 93000 1000 2000 0x00000000]
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+	Line[185000 50000 185000 93000 1000 2000 0x00000000]
+	Line[184500 23500 189000 28000 1000 2000 0x00000000]
+	Line[189000 28000 189000 93000 1000 2000 0x00000000]
+	Line[194500 23500 193000 25000 1000 2000 0x00000000]
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+	Line[254500 23500 216922 61078 1000 2000 0x00000000]
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+	Line[205000 43000 205000 91000 1000 2000 0x00000000]
+	Line[174000 69000 174000 92000 1000 2000 0x00000000]
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+		[54500 6500] [289500 6500] [289500 0] [54500 0] 
+	)
+	Polygon(0x00000010)
+	(
+		[71500 60500] [260500 60500] [260500 9000] [71500 9000] 
+	)
+	Polygon(0x00000010)
+	(
+		[2500 12000] [61500 12000] [61500 0] [2500 0] 
+	)
+)
+Layer(5 "GND-comp")
+(
+)
+Layer(6 "Vcc-comp")
+(
+)
+Layer(7 "GND")
+(
+)
+Layer(8 "internal")
+(
+)
+Layer(9 "silk")
+(
+	Text[265000 18500 0 100 "BACK SILK" 0x00000080]
+)
+Layer(10 "silk")
+(
+	Text[57000 2000 0 100 "GND" 0x00000000]
+	Text[265000 9500 0 100 "SILK" 0x00000000]
+	Text[157000 2000 0 100 "GND" 0x00000000]
+	Text[159800 35300 2 78 "8" 0x00000000]
+	Text[182900 31800 0 78 "7" 0x00000000]
+	Text[254100 31600 0 78 "0" 0x00000000]
+	Text[87600 33500 0 78 "15" 0x00000000]
+)
+NetList()
+(
+	Net("unnamed_net9" "(unknown)")
+	(
+		Connect("R9-2")
+		Connect("R16-1")
+		Connect("U4-6")
+	)
+	Net("unnamed_net8" "(unknown)")
+	(
+		Connect("R13-1")
+		Connect("R14-1")
+		Connect("C4-2")
+		Connect("U4-5")
+	)
+	Net("unnamed_net7" "(unknown)")
+	(
+		Connect("R7-2")
+		Connect("R8-1")
+		Connect("U4-2")
+	)
+	Net("unnamed_net6" "(unknown)")
+	(
+		Connect("R11-1")
+		Connect("R12-1")
+		Connect("C3-2")
+		Connect("U4-3")
+	)
+	Net("SDA_5V" "(unknown)")
+	(
+		Connect("R4-1")
+		Connect("R3-2")
+		Connect("Q2-3")
+		Connect("U2-12")
+	)
+	Net("SCL_5V" "(unknown)")
+	(
+		Connect("R2-1")
+		Connect("R1-2")
+		Connect("Q1-3")
+		Connect("U2-11")
+	)
+	Net("unnamed_net5" "(unknown)")
+	(
+		Connect("R6-1")
+		Connect("R5-2")
+		Connect("U2-13")
+	)
+	Net("5V_RF" "(unknown)")
+	(
+		Connect("C82-1")
+		Connect("U3-3")
+		Connect("U4-8")
+		Connect("R4-2")
+		Connect("R2-2")
+		Connect("C108-1")
+		Connect("C107-1")
+		Connect("C106-1")
+		Connect("C105-1")
+		Connect("C104-1")
+		Connect("C103-1")
+		Connect("C102-1")
+		Connect("C101-1")
+		Connect("U2-6")
+		Connect("U2-10")
+		Connect("U2-15")
+		Connect("U2-3")
+	)
+	Net("ifagc" "(unknown)")
+	(
+		Connect("R7-1")
+		Connect("U4-1")
+		Connect("U2-16")
+	)
+	Net("rfagc" "(unknown)")
+	(
+		Connect("R9-1")
+		Connect("U4-7")
+		Connect("U2-7")
+	)
+	Net("unnamed_net4" "(unknown)")
+	(
+		Connect("U2-18")
+		Connect("R17-1")
+	)
+	Net("unnamed_net3" "(unknown)")
+	(
+		Connect("C2-2")
+		Connect("R17-2")
+	)
+	Net("unnamed_net2" "(unknown)")
+	(
+		Connect("U2-17")
+		Connect("R10-1")
+	)
+	Net("unnamed_net1" "(unknown)")
+	(
+		Connect("C1-2")
+		Connect("R10-2")
+	)
+	Net("AUX_ADC_B1" "(unknown)")
+	(
+		Connect("J2-61")
+	)
+	Net("AUX_ADC_A1" "(unknown)")
+	(
+		Connect("J2-59")
+	)
+	Net("AUX_ADC_REF" "(unknown)")
+	(
+		Connect("J2-57")
+	)
+	Net("AUX_DAC_C" "(unknown)")
+	(
+		Connect("J2-55")
+	)
+	Net("AUX_DAC_B" "(unknown)")
+	(
+		Connect("R14-2")
+		Connect("J2-53")
+	)
+	Net("AUX_DAC_A" "(unknown)")
+	(
+		Connect("R12-2")
+		Connect("J2-51")
+	)
+	Net("AUX_DAC_D" "(unknown)")
+	(
+		Connect("J2-49")
+	)
+	Net("SEN_RX" "(unknown)")
+	(
+		Connect("J2-35")
+	)
+	Net("VINP_A" "(unknown)")
+	(
+		Connect("C1-1")
+		Connect("C5-1")
+		Connect("J2-62")
+	)
+	Net("VINN_A" "(unknown)")
+	(
+		Connect("C2-1")
+		Connect("C6-1")
+		Connect("J2-60")
+	)
+	Net("VREF" "(unknown)")
+	(
+		Connect("J2-56")
+	)
+	Net("VINN_B" "(unknown)")
+	(
+		Connect("J2-52")
+	)
+	Net("VINP_B" "(unknown)")
+	(
+		Connect("J2-50")
+	)
+	Net("AVDD" "(unknown)")
+	(
+		Connect("J2-45")
+		Connect("J2-43")
+		Connect("J2-46")
+		Connect("J2-44")
+	)
+	Net("AGND" "(unknown)")
+	(
+		Connect("C105-2")
+		Connect("C106-2")
+		Connect("C107-2")
+		Connect("C108-2")
+		Connect("C103-2")
+		Connect("C104-2")
+		Connect("C101-2")
+		Connect("C102-2")
+		Connect("C83-1")
+		Connect("C82-2")
+		Connect("U3-4")
+		Connect("U3-2")
+		Connect("C4-1")
+		Connect("C3-1")
+		Connect("R16-2")
+		Connect("R8-2")
+		Connect("U4-4")
+		Connect("R5-1")
+		Connect("U2-24")
+		Connect("U2-23")
+		Connect("U2-22")
+		Connect("U2-21")
+		Connect("U2-5")
+		Connect("C6-2")
+		Connect("C5-2")
+		Connect("U1-4")
+		Connect("U1-7")
+		Connect("J2-63")
+		Connect("J2-47")
+		Connect("J2-41")
+		Connect("J2-64")
+		Connect("J2-58")
+		Connect("J2-54")
+		Connect("J2-48")
+		Connect("J2-42")
+	)
+	Net("io_rx_00" "(unknown)")
+	(
+		Connect("R11-2")
+		Connect("J24-15")
+		Connect("J2-36")
+	)
+	Net("io_rx_01" "(unknown)")
+	(
+		Connect("R13-2")
+		Connect("J24-13")
+		Connect("J2-34")
+	)
+	Net("io_rx_02" "(unknown)")
+	(
+		Connect("J24-11")
+		Connect("J2-32")
+	)
+	Net("io_rx_03" "(unknown)")
+	(
+		Connect("J24-9")
+		Connect("J2-30")
+	)
+	Net("io_rx_04" "(unknown)")
+	(
+		Connect("J24-7")
+		Connect("J2-28")
+	)
+	Net("SDI" "(unknown)")
+	(
+		Connect("J2-33")
+	)
+	Net("SDO" "(unknown)")
+	(
+		Connect("J2-31")
+	)
+	Net("SCLK" "(unknown)")
+	(
+		Connect("J2-29")
+	)
+	Net("RESET" "(unknown)")
+	(
+		Connect("J2-27")
+	)
+	Net("io_rx_05" "(unknown)")
+	(
+		Connect("J24-5")
+		Connect("J2-26")
+	)
+	Net("RS232_RXD" "(unknown)")
+	(
+		Connect("J2-25")
+	)
+	Net("io_rx_06" "(unknown)")
+	(
+		Connect("J24-3")
+		Connect("J2-24")
+	)
+	Net("RS232_TXD" "(unknown)")
+	(
+		Connect("J2-23")
+	)
+	Net("io_rx_07" "(unknown)")
+	(
+		Connect("J24-1")
+		Connect("J2-22")
+	)
+	Net("I2C_A0" "(unknown)")
+	(
+		Connect("U1-1")
+		Connect("J2-21")
+	)
+	Net("io_rx_08" "(unknown)")
+	(
+		Connect("J25-15")
+		Connect("J2-20")
+	)
+	Net("I2C_A1" "(unknown)")
+	(
+		Connect("R6-2")
+		Connect("U1-2")
+		Connect("J2-19")
+	)
+	Net("io_rx_09" "(unknown)")
+	(
+		Connect("J25-13")
+		Connect("J2-18")
+	)
+	Net("SDA" "(unknown)")
+	(
+		Connect("R3-1")
+		Connect("Q2-2")
+		Connect("U1-5")
+		Connect("J2-17")
+	)
+	Net("io_rx_10" "(unknown)")
+	(
+		Connect("J25-11")
+		Connect("J2-16")
+	)
+	Net("SCL" "(unknown)")
+	(
+		Connect("R1-1")
+		Connect("Q1-2")
+		Connect("U1-6")
+		Connect("J2-15")
+	)
+	Net("io_rx_11" "(unknown)")
+	(
+		Connect("J25-9")
+		Connect("J2-14")
+	)
+	Net("io_rx_12" "(unknown)")
+	(
+		Connect("J25-7")
+		Connect("J2-12")
+	)
+	Net("io_rx_13" "(unknown)")
+	(
+		Connect("J25-5")
+		Connect("J2-10")
+	)
+	Net("io_rx_14" "(unknown)")
+	(
+		Connect("J25-3")
+		Connect("J2-8")
+	)
+	Net("DVDD" "(unknown)")
+	(
+		Connect("Q2-1")
+		Connect("Q1-1")
+		Connect("U1-8")
+		Connect("U1-3")
+		Connect("J2-9")
+		Connect("J2-7")
+	)
+	Net("io_rx_15" "(unknown)")
+	(
+		Connect("J25-1")
+		Connect("J2-6")
+	)
+	Net("6V" "(unknown)")
+	(
+		Connect("C83-2")
+		Connect("U3-1")
+		Connect("J2-5")
+		Connect("J2-3")
+	)
+	Net("GND" "(unknown)")
+	(
+		Connect("J25-6")
+		Connect("J25-4")
+		Connect("J25-14")
+		Connect("J25-12")
+		Connect("J25-10")
+		Connect("J25-16")
+		Connect("J25-8")
+		Connect("J25-2")
+		Connect("J24-6")
+		Connect("J24-4")
+		Connect("J24-14")
+		Connect("J24-12")
+		Connect("J24-10")
+		Connect("J24-16")
+		Connect("J24-8")
+		Connect("J24-2")
+		Connect("J2-37")
+		Connect("J2-38")
+		Connect("J2-2")
+		Connect("J2-1")
+	)
+)
diff --git a/usrp-hw/tvrx/tvrx.prj b/usrp-hw/tvrx/tvrx.prj
new file mode 100644
index 000000000..fd0810781
--- /dev/null
+++ b/usrp-hw/tvrx/tvrx.prj
@@ -0,0 +1,6 @@
+# List all schematics
+schematics tvrx.sch
+
+output-name tvrx
+
+elements-dir ../pkg/newlib
diff --git a/usrp-hw/tvrx/tvrx.sch b/usrp-hw/tvrx/tvrx.sch
new file mode 100644
index 000000000..c2cb9b332
--- /dev/null
+++ b/usrp-hw/tvrx/tvrx.sch
@@ -0,0 +1,1073 @@
+v 20050820 1
+C 83700 45200 1 180 1 pmc64.sym
+{
+T 84400 32000 5 10 1 1 0 2 1
+refdes=J2
+T 83700 45200 5 10 0 1 90 6 1
+footprint=PMC-REVERSE
+}
+N 85200 40100 86900 40100 4
+{
+T 85500 40100 5 10 1 1 0 0 1
+netname=RS232_RXD
+}
+N 85200 40500 86900 40500 4
+{
+T 85500 40500 5 10 1 1 0 0 1
+netname=RS232_TXD
+}
+C 83600 32300 1 90 0 generic-power.sym
+{
+T 83350 32500 5 10 1 1 90 3 1
+net=AGND:1
+}
+N 83600 32500 83800 32500 4
+N 85200 41300 86500 41300 4
+{
+T 85600 41300 5 10 1 1 0 0 1
+netname=I2C_A1
+}
+C 85400 32700 1 270 0 generic-power.sym
+{
+T 85650 32500 5 10 1 1 270 3 1
+net=AGND:1
+}
+N 85400 32500 85200 32500 4
+N 85200 38100 86400 38100 4
+{
+T 85300 38100 5 10 1 1 0 0 1
+netname=SEN_RX
+}
+C 83600 36700 1 90 0 generic-power.sym
+{
+T 83350 36900 5 10 1 1 90 3 1
+net=AGND:1
+}
+N 83600 36900 83800 36900 4
+C 85400 37100 1 270 0 generic-power.sym
+{
+T 85650 36900 5 10 1 1 270 3 1
+net=AGND:1
+}
+N 85400 36900 85200 36900 4
+N 85200 33300 86800 33300 4
+{
+T 85200 33300 5 10 1 1 0 0 1
+netname=AUX_ADC_A1
+}
+N 85200 32900 86800 32900 4
+{
+T 85200 32900 5 10 1 1 0 0 1
+netname=AUX_ADC_B1
+}
+C 83600 33500 1 90 0 generic-power.sym
+{
+T 83350 33700 5 10 1 1 90 3 1
+net=AGND:1
+}
+N 83600 33700 83800 33700 4
+C 83600 34300 1 90 0 generic-power.sym
+{
+T 83350 34500 5 10 1 1 90 3 1
+net=AGND:1
+}
+N 83600 34500 83800 34500 4
+C 83600 35500 1 90 0 generic-power.sym
+{
+T 83350 35700 5 10 1 1 90 3 1
+net=AGND:1
+}
+N 83600 35700 83800 35700 4
+N 82200 32900 83800 32900 4
+{
+T 82200 32900 5 10 1 1 0 0 1
+netname=VINP_A
+}
+N 82200 33300 83800 33300 4
+{
+T 82200 33300 5 10 1 1 0 0 1
+netname=VINN_A
+}
+N 82200 35300 83800 35300 4
+{
+T 82200 35300 5 10 1 1 0 0 1
+netname=VINP_B
+}
+N 82200 34900 83800 34900 4
+{
+T 82200 34900 5 10 1 1 0 0 1
+netname=VINN_B
+}
+N 83800 34100 82200 34100 4
+{
+T 82300 34100 5 10 1 1 0 0 1
+netname=VREF
+}
+C 85400 35900 1 270 0 generic-power.sym
+{
+T 85650 35700 5 10 1 1 270 3 1
+net=AGND:1
+}
+N 85400 35700 85200 35700 4
+C 86000 36300 1 270 0 generic-power.sym
+{
+T 86250 36100 5 10 1 1 270 3 1
+net=AVDD:1
+}
+N 85200 36500 85700 36500 4
+N 85200 36100 86000 36100 4
+C 85700 36700 1 270 0 generic-power.sym
+{
+T 85950 36500 5 10 1 1 270 3 1
+net=AVDD:1
+}
+C 85900 44700 1 270 0 generic-power.sym
+{
+T 86150 44500 5 10 1 1 270 3 1
+net=6V:1
+}
+C 83000 36300 1 90 1 generic-power.sym
+{
+T 82750 36100 5 10 1 1 90 3 1
+net=AVDD:1
+}
+N 83800 36100 83000 36100 4
+N 83800 36500 83300 36500 4
+C 83300 36700 1 90 1 generic-power.sym
+{
+T 83050 36500 5 10 1 1 90 3 1
+net=AVDD:1
+}
+N 85200 44500 85900 44500 4
+N 85200 44100 85700 44100 4
+C 85700 43500 1 270 0 generic-power.sym
+{
+T 85950 43300 5 10 1 1 270 3 1
+net=DVDD:1
+}
+N 85200 43300 85700 43300 4
+N 85200 43700 85500 43700 4
+N 85700 44100 85700 44500 4
+N 85500 43700 85500 43300 4
+N 81800 44100 83800 44100 4
+{
+T 82100 44100 5 10 1 1 0 0 1
+netname=io_rx_15
+}
+N 81800 43700 83800 43700 4
+{
+T 82100 43700 5 10 1 1 0 0 1
+netname=io_rx_14
+}
+N 81800 42500 83800 42500 4
+{
+T 82100 42500 5 10 1 1 0 0 1
+netname=io_rx_11
+}
+N 81800 43300 83800 43300 4
+{
+T 82100 43300 5 10 1 1 0 0 1
+netname=io_rx_13
+}
+N 81800 42900 83800 42900 4
+{
+T 82100 42900 5 10 1 1 0 0 1
+netname=io_rx_12
+}
+N 81800 41300 83800 41300 4
+{
+T 82100 41300 5 10 1 1 0 0 1
+netname=io_rx_08
+}
+N 81800 42100 83800 42100 4
+{
+T 82100 42100 5 10 1 1 0 0 1
+netname=io_rx_10
+}
+N 81800 41700 83800 41700 4
+{
+T 82100 41700 5 10 1 1 0 0 1
+netname=io_rx_09
+}
+N 81800 40100 83800 40100 4
+{
+T 82100 40100 5 10 1 1 0 0 1
+netname=io_rx_05
+}
+N 81800 40900 83800 40900 4
+{
+T 82100 40900 5 10 1 1 0 0 1
+netname=io_rx_07
+}
+N 81800 40500 83800 40500 4
+{
+T 82100 40500 5 10 1 1 0 0 1
+netname=io_rx_06
+}
+N 81800 38900 83800 38900 4
+{
+T 82100 38900 5 10 1 1 0 0 1
+netname=io_rx_02
+}
+N 81800 39700 83800 39700 4
+{
+T 82100 39700 5 10 1 1 0 0 1
+netname=io_rx_04
+}
+N 81800 39300 83800 39300 4
+{
+T 82100 39300 5 10 1 1 0 0 1
+netname=io_rx_03
+}
+N 81800 38100 83800 38100 4
+{
+T 82100 38100 5 10 1 1 0 0 1
+netname=io_rx_00
+}
+N 81800 38500 83800 38500 4
+{
+T 82100 38500 5 10 1 1 0 0 1
+netname=io_rx_01
+}
+C 65600 29400 0 0 0 title-bordered-C.sym
+T 82500 30300 5 10 1 1 0 0 1
+date=$Date: 2005/12/19 02:52:55 $
+T 84400 30000 5 10 1 1 0 0 1
+rev=$Revision: 1.5 $
+T 84500 29700 5 10 1 1 0 0 1
+auth=$Author: matt $
+T 80300 30000 5 10 1 1 0 0 1
+fname=$Source: /opt/usrp-hw-cvs/usrp-hw/tvrx/tvrx.sch,v $
+T 83700 30700 8 14 1 1 0 4 1
+title=TV Tuner Daughterboard
+T 81300 29700 9 10 1 0 0 0 1
+1
+T 82100 29700 9 10 1 0 0 0 1
+1
+N 85200 42100 86300 42100 4
+{
+T 85500 42100 5 10 1 1 0 0 1
+netname=SCL
+}
+N 85200 41700 86300 41700 4
+{
+T 85500 41700 5 10 1 1 0 0 1
+netname=SDA
+}
+N 85200 39300 86600 39300 4
+{
+T 85600 39300 5 10 1 1 0 0 1
+netname=SCLK
+}
+N 85200 38900 86600 38900 4
+{
+T 85600 38900 5 10 1 1 0 0 1
+netname=SDO
+}
+N 85200 38500 86600 38500 4
+{
+T 85600 38500 5 10 1 1 0 0 1
+netname=SDI
+}
+N 85200 34900 86900 34900 4
+{
+T 85400 34900 5 10 1 1 0 0 1
+netname=AUX_DAC_A
+}
+N 85200 34500 86900 34500 4
+{
+T 85400 34500 5 10 1 1 0 0 1
+netname=AUX_DAC_B
+}
+N 85200 34100 86900 34100 4
+{
+T 85400 34100 5 10 1 1 0 0 1
+netname=AUX_DAC_C
+}
+N 85200 33700 86900 33700 4
+{
+T 85300 33700 5 10 1 1 0 0 1
+netname=AUX_ADC_REF
+}
+N 85200 35300 86900 35300 4
+{
+T 85400 35300 5 10 1 1 0 0 1
+netname=AUX_DAC_D
+}
+C 72500 42900 1 0 0 24Cxx-1.sym
+{
+T 73000 44100 5 10 1 1 0 0 1
+refdes=U1
+T 72500 42900 5 10 0 1 0 0 1
+footprint=SO8
+T 72800 42700 5 10 1 1 0 0 1
+device=24LC025B
+T 72800 42300 5 10 1 1 0 0 1
+net=AGND:4
+T 72800 42500 5 10 1 1 0 0 1
+net=DVDD:8
+}
+N 73800 43200 75200 43200 4
+{
+T 74700 43200 5 10 1 1 0 0 1
+netname=SCL
+}
+N 73800 43000 75200 43000 4
+{
+T 74700 43000 5 10 1 1 0 0 1
+netname=SDA
+}
+N 73800 43400 74000 43400 4
+N 85200 40900 86500 40900 4
+{
+T 85600 40900 5 10 1 1 0 0 1
+netname=I2C_A0
+}
+N 71500 43400 72500 43400 4
+{
+T 71600 43400 5 10 1 1 0 0 1
+netname=I2C_A1
+}
+N 71500 43600 72500 43600 4
+{
+T 71600 43600 5 10 1 1 0 0 1
+netname=I2C_A0
+}
+C 71500 43000 1 90 0 generic-power.sym
+{
+T 71250 43200 5 10 1 1 90 3 1
+net=DVDD:1
+}
+N 71500 43200 72500 43200 4
+N 69200 38200 70200 38200 4
+{
+T 69200 38200 5 10 1 1 0 0 1
+netname=VINP_A
+}
+N 69600 37800 70600 37800 4
+{
+T 69600 37800 5 10 1 1 0 0 1
+netname=VINN_A
+}
+C 72200 38100 1 0 1 resistor-1.sym
+{
+T 71200 38500 5 10 1 1 180 6 1
+refdes=R10
+T 71900 38500 5 10 1 1 180 6 1
+value=0
+T 72200 38100 5 10 0 1 0 6 1
+footprint=0603
+}
+C 72600 37700 1 0 1 resistor-1.sym
+{
+T 72000 38100 5 10 1 1 180 6 1
+refdes=R17
+T 72400 38100 5 10 1 1 180 6 1
+value=0
+T 72600 37700 5 10 0 1 0 6 1
+footprint=0603
+}
+C 69200 38000 1 0 1 capacitor-1.sym
+{
+T 68600 38300 5 10 1 1 0 6 1
+refdes=C5
+T 68600 37900 5 10 1 1 0 6 1
+value=10pF
+T 69200 38000 5 10 0 1 90 2 1
+footprint=0603
+}
+C 69600 37600 1 0 1 capacitor-1.sym
+{
+T 69000 37900 5 10 1 1 0 6 1
+refdes=C6
+T 69000 37500 5 10 1 1 0 6 1
+value=10pF
+T 69600 37600 5 10 0 1 90 2 1
+footprint=0603
+}
+C 68100 38000 1 90 0 generic-power.sym
+{
+T 67850 38200 5 10 1 1 270 5 1
+net=AGND:1
+}
+N 68300 38200 68100 38200 4
+C 68500 37600 1 90 0 generic-power.sym
+{
+T 68250 37800 5 10 1 1 270 5 1
+net=AGND:1
+}
+N 68700 37800 68500 37800 4
+N 72800 38200 72200 38200 4
+N 72800 37800 72600 37800 4
+T 81100 45500 9 20 1 0 0 0 1
+REVERSE PMC on BOTTOM!!!!
+N 86600 39700 85200 39700 4
+{
+T 86200 39700 5 10 1 1 0 6 1
+netname=RESET
+}
+C 79700 35400 1 0 0 header16-1.sym
+{
+T 80200 38700 5 10 1 1 0 0 1
+refdes=J24
+T 79700 35400 5 10 0 1 0 0 1
+footprint=CONNECTOR 8 2
+}
+C 79700 31400 1 0 0 header16-1.sym
+{
+T 80200 34700 5 10 1 1 0 0 1
+refdes=J25
+T 79700 31400 5 10 0 1 0 0 1
+footprint=CONNECTOR 8 2
+}
+N 81100 37200 81400 37200 4
+C 81700 37100 1 90 0 gnd-1.sym
+N 81100 38400 81300 38400 4
+N 81300 38400 81300 37200 4
+N 81300 37200 81300 35600 4
+N 81300 35600 81100 35600 4
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+N 81100 36800 81300 36800 4
+N 81100 36400 81300 36400 4
+N 81100 36000 81300 36000 4
+N 81100 33200 81400 33200 4
+C 81700 33100 1 90 0 gnd-1.sym
+N 81100 34400 81300 34400 4
+N 81300 34400 81300 33200 4
+N 81300 33200 81300 31600 4
+N 81300 31600 81100 31600 4
+N 81100 34000 81300 34000 4
+N 81100 33600 81300 33600 4
+N 81100 32800 81300 32800 4
+N 81100 32400 81300 32400 4
+N 81100 32000 81300 32000 4
+N 78000 34400 79700 34400 4
+{
+T 78500 34400 5 10 1 1 0 0 1
+netname=io_rx_15
+}
+N 78000 32800 79700 32800 4
+{
+T 78500 32800 5 10 1 1 0 0 1
+netname=io_rx_11
+}
+N 78000 33600 79700 33600 4
+{
+T 78500 33600 5 10 1 1 0 0 1
+netname=io_rx_13
+}
+N 78000 32000 79700 32000 4
+{
+T 78500 32000 5 10 1 1 0 0 1
+netname=io_rx_09
+}
+N 78100 37600 79700 37600 4
+{
+T 78500 37600 5 10 1 1 0 0 1
+netname=io_rx_05
+}
+N 78100 38400 79700 38400 4
+{
+T 78500 38400 5 10 1 1 0 0 1
+netname=io_rx_07
+}
+N 78100 36800 79700 36800 4
+{
+T 78500 36800 5 10 1 1 0 0 1
+netname=io_rx_03
+}
+N 78100 36000 79700 36000 4
+{
+T 78500 36000 5 10 1 1 0 0 1
+netname=io_rx_01
+}
+N 78000 34000 79700 34000 4
+{
+T 78500 34000 5 10 1 1 0 0 1
+netname=io_rx_14
+}
+N 78000 33200 79700 33200 4
+{
+T 78500 33200 5 10 1 1 0 0 1
+netname=io_rx_12
+}
+N 78000 31600 79700 31600 4
+{
+T 78500 31600 5 10 1 1 0 0 1
+netname=io_rx_08
+}
+N 78000 32400 79700 32400 4
+{
+T 78500 32400 5 10 1 1 0 0 1
+netname=io_rx_10
+}
+N 78100 38000 79700 38000 4
+{
+T 78500 38000 5 10 1 1 0 0 1
+netname=io_rx_06
+}
+N 78100 36400 79700 36400 4
+{
+T 78500 36400 5 10 1 1 0 0 1
+netname=io_rx_02
+}
+N 78100 37200 79700 37200 4
+{
+T 78500 37200 5 10 1 1 0 0 1
+netname=io_rx_04
+}
+N 78100 35600 79700 35600 4
+{
+T 78500 35600 5 10 1 1 0 0 1
+netname=io_rx_00
+}
+C 72700 34100 1 0 0 mt4937di5.sym
+{
+T 73700 40900 5 10 1 1 0 6 1
+refdes=U2
+}
+C 75400 40600 1 0 0 generic-power.sym
+{
+T 75600 40850 5 10 1 1 180 5 1
+net=5V_RF:1
+}
+N 74800 40200 75600 40200 4
+N 75600 37700 75600 40600 4
+N 75600 39000 74800 39000 4
+N 75600 39400 74800 39400 4
+N 75600 39800 74800 39800 4
+N 72800 40200 71500 40200 4
+{
+T 71600 40200 5 10 1 1 0 0 1
+netname=rfagc
+}
+N 72800 39800 71500 39800 4
+{
+T 71600 39800 5 10 1 1 0 0 1
+netname=ifagc
+}
+N 66100 44400 66700 44400 4
+{
+T 66300 44400 5 10 1 1 0 0 1
+netname=SCL
+}
+N 68200 41300 69200 41300 4
+{
+T 68300 41300 5 10 1 1 0 0 1
+netname=I2C_A1
+}
+C 66700 44900 1 270 0 nmos-sot23.sym
+{
+T 67100 44900 5 10 1 1 0 0 1
+refdes=Q1
+}
+C 66700 45000 1 0 0 generic-power.sym
+{
+T 66900 45250 5 10 1 1 0 3 1
+net=DVDD:1
+}
+C 67700 45500 1 0 0 generic-power.sym
+{
+T 67900 45750 5 10 1 1 180 5 1
+net=5V_RF:1
+}
+N 66900 45000 66900 44900 4
+C 66700 44000 1 0 0 resistor-1.sym
+{
+T 67100 43900 5 10 1 1 270 0 1
+value=NONE
+T 66700 44000 5 10 0 1 0 0 1
+footprint=0603
+T 67300 43900 5 10 1 1 270 0 1
+refdes=R1
+}
+C 68000 44500 1 90 0 resistor-1.sym
+{
+T 68100 44900 5 10 1 1 0 0 1
+value=2.2K
+T 68000 44500 5 10 0 1 90 0 1
+footprint=0603
+T 68100 45100 5 10 1 1 0 0 1
+refdes=R2
+}
+N 66500 44400 66500 44100 4
+N 67500 44400 68800 44400 4
+{
+T 68000 44400 5 10 1 1 0 0 1
+netname=SCL_5V
+}
+N 67900 45400 67900 45500 4
+N 67800 44100 67800 44400 4
+N 67900 44500 67900 44400 4
+N 67800 44100 67600 44100 4
+N 66700 44100 66500 44100 4
+N 67800 42900 68400 42900 4
+{
+T 68000 42900 5 10 1 1 0 0 1
+netname=SDA
+}
+C 68400 43400 1 270 0 nmos-sot23.sym
+{
+T 68800 43400 5 10 1 1 0 0 1
+refdes=Q2
+}
+C 68400 43500 1 0 0 generic-power.sym
+{
+T 68600 43750 5 10 1 1 0 3 1
+net=DVDD:1
+}
+C 69400 44000 1 0 0 generic-power.sym
+{
+T 69600 44250 5 10 1 1 180 5 1
+net=5V_RF:1
+}
+N 68600 43500 68600 43400 4
+C 68400 42500 1 0 0 resistor-1.sym
+{
+T 68800 42400 5 10 1 1 270 0 1
+value=NONE
+T 68400 42500 5 10 0 1 0 0 1
+footprint=0603
+T 69000 42400 5 10 1 1 270 0 1
+refdes=R3
+}
+C 69700 43000 1 90 0 resistor-1.sym
+{
+T 69800 43400 5 10 1 1 0 0 1
+value=2.2K
+T 69700 43000 5 10 0 1 90 0 1
+footprint=0603
+T 69800 43600 5 10 1 1 0 0 1
+refdes=R4
+}
+N 68200 42900 68200 42600 4
+N 69200 42900 70500 42900 4
+{
+T 69700 42900 5 10 1 1 0 0 1
+netname=SDA_5V
+}
+N 69600 43900 69600 44000 4
+N 69500 42600 69500 42900 4
+N 69600 43000 69600 42900 4
+N 69500 42600 69300 42600 4
+N 68400 42600 68200 42600 4
+N 71500 39000 72800 39000 4
+{
+T 72000 39000 5 10 1 1 0 0 1
+netname=SCL_5V
+}
+N 71500 38600 72800 38600 4
+{
+T 72000 38600 5 10 1 1 0 0 1
+netname=SDA_5V
+}
+T 70700 44900 9 20 1 0 0 0 1
+Add 470 pF and 4.7uF to each VSx
+C 75300 34500 1 180 0 generic-power.sym
+{
+T 75100 34250 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 75100 35800 74800 35800 4
+N 75100 35400 74800 35400 4
+N 75100 35000 74800 35000 4
+N 75100 34600 74800 34600 4
+C 70200 38400 1 180 1 capacitor-1.sym
+{
+T 70800 38300 5 10 1 1 0 0 1
+refdes=C1
+T 70800 38000 5 10 1 1 0 0 1
+value=.1uF
+T 70200 38400 5 10 0 1 270 2 1
+footprint=0603
+}
+C 70600 38000 1 180 1 capacitor-1.sym
+{
+T 71200 37900 5 10 1 1 0 0 1
+refdes=C2
+T 71200 37600 5 10 1 1 0 0 1
+value=.1uF
+T 70600 38000 5 10 0 1 270 2 1
+footprint=0603
+}
+N 71500 37800 71700 37800 4
+N 71100 38200 71300 38200 4
+C 69300 39200 1 90 0 resistor-1.sym
+{
+T 69400 39600 5 10 1 1 0 0 1
+value=1K
+T 69300 39200 5 10 0 1 90 0 1
+footprint=0603
+T 69400 39800 5 10 1 1 0 0 1
+refdes=R5
+}
+C 69300 40300 1 90 0 resistor-1.sym
+{
+T 69400 40700 5 10 1 1 0 0 1
+value=1.6K
+T 69300 40300 5 10 0 1 90 0 1
+footprint=0603
+T 69400 40900 5 10 1 1 0 0 1
+refdes=R6
+}
+C 69400 39000 1 180 0 generic-power.sym
+{
+T 69200 38750 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 69200 39000 69200 39200 4
+N 69200 40100 69200 40300 4
+N 69200 41200 69200 41300 4
+N 69200 40200 70200 40200 4
+N 70200 40200 70200 39400 4
+N 70200 39400 72800 39400 4
+N 66600 34000 68000 34000 4
+{
+T 66700 34000 5 10 1 1 0 0 1
+netname=AUX_DAC_A
+}
+N 71100 31600 72500 31600 4
+{
+T 71300 31600 5 10 1 1 0 0 1
+netname=AUX_DAC_B
+}
+C 69200 34500 1 0 0 dual-opamp-1.sym
+{
+T 70000 34500 5 10 1 1 0 0 1
+refdes=U4
+T 69200 34500 5 10 0 1 0 0 1
+slot=1
+}
+C 73700 32100 1 0 0 dual-opamp-1.sym
+{
+T 74500 32200 5 10 1 1 0 0 1
+refdes=U4
+T 73700 32100 5 10 0 1 0 0 1
+slot=2
+T 74100 32400 5 10 0 1 0 0 1
+footprint=SO8
+}
+C 70200 35900 1 0 1 resistor-1.sym
+{
+T 69600 36300 5 10 1 1 180 6 1
+refdes=R7
+T 70000 36300 5 10 1 1 180 6 1
+value=10K
+T 70200 35900 5 10 0 1 0 6 1
+footprint=0603
+}
+C 69000 35000 1 0 1 resistor-1.sym
+{
+T 68400 35400 5 10 1 1 180 6 1
+refdes=R8
+T 68800 35400 5 10 1 1 180 6 1
+value=10K
+T 69000 35000 5 10 0 1 0 6 1
+footprint=0603
+}
+C 67900 34900 1 90 0 generic-power.sym
+{
+T 67650 35100 5 10 1 1 90 3 1
+net=AGND:1
+}
+C 69500 35400 1 0 0 generic-power.sym
+{
+T 69700 35650 5 10 1 1 180 5 1
+net=5V_RF:1
+}
+C 69900 34400 1 180 0 generic-power.sym
+{
+T 69700 34150 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 69700 34400 69700 34500 4
+N 69700 35300 69700 35400 4
+N 70200 36000 70400 36000 4
+N 70400 36000 70400 34900 4
+N 70200 34900 71000 34900 4
+{
+T 70500 34900 5 10 1 1 0 0 1
+netname=ifagc
+}
+N 69200 35100 69000 35100 4
+N 69100 35100 69100 36000 4
+N 69100 36000 69300 36000 4
+N 67900 35100 68100 35100 4
+C 74700 33100 1 0 1 resistor-1.sym
+{
+T 74100 33500 5 10 1 1 180 6 1
+refdes=R9
+T 74500 33500 5 10 1 1 180 6 1
+value=10K
+T 74700 33100 5 10 0 1 0 6 1
+footprint=0603
+}
+C 73500 32600 1 0 1 resistor-1.sym
+{
+T 72900 33000 5 10 1 1 180 6 1
+refdes=R16
+T 73300 33000 5 10 1 1 180 6 1
+value=10K
+T 73500 32600 5 10 0 1 0 6 1
+footprint=0603
+}
+C 72400 32500 1 90 0 generic-power.sym
+{
+T 72150 32700 5 10 1 1 90 3 1
+net=AGND:1
+}
+N 74700 32500 75500 32500 4
+{
+T 75000 32500 5 10 1 1 0 0 1
+netname=rfagc
+}
+N 73700 32700 73500 32700 4
+N 73600 32700 73600 33200 4
+N 72400 32700 72600 32700 4
+N 73600 33200 73800 33200 4
+N 74700 33200 74900 33200 4
+N 74900 33200 74900 32500 4
+N 74800 36200 75100 36200 4
+N 75100 34500 75100 36200 4
+N 66600 34500 68000 34500 4
+{
+T 66900 34500 5 10 1 1 0 0 1
+netname=io_rx_00
+}
+N 71300 32100 72500 32100 4
+{
+T 71600 32100 5 10 1 1 0 0 1
+netname=io_rx_01
+}
+C 68900 32900 1 270 1 capacitor-1.sym
+{
+T 69000 33500 5 10 1 1 90 0 1
+refdes=C3
+T 69300 33500 5 10 1 1 90 0 1
+value=.1uF
+T 68900 32900 5 10 0 1 0 2 1
+footprint=0603
+}
+C 68900 34400 1 0 1 resistor-1.sym
+{
+T 68100 34800 5 10 1 1 180 6 1
+refdes=R11
+T 68400 34800 5 10 1 1 180 6 1
+value=NONE
+T 68900 34400 5 10 0 1 0 6 1
+footprint=0603
+}
+C 68900 33900 1 0 1 resistor-1.sym
+{
+T 68100 34300 5 10 1 1 180 6 1
+refdes=R12
+T 68600 34300 5 10 1 1 180 6 1
+value=10K
+T 68900 33900 5 10 0 1 0 6 1
+footprint=0603
+}
+N 68900 34000 69100 34000 4
+N 69100 34700 69200 34700 4
+N 68900 34500 69100 34500 4
+C 69300 32700 1 180 0 generic-power.sym
+{
+T 69100 32450 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 69100 32700 69100 32900 4
+N 69100 33800 69100 34700 4
+C 73400 30500 1 270 1 capacitor-1.sym
+{
+T 73500 31100 5 10 1 1 90 0 1
+refdes=C4
+T 73800 31100 5 10 1 1 90 0 1
+value=.1uF
+T 73400 30500 5 10 0 1 0 2 1
+footprint=0603
+}
+C 73400 32000 1 0 1 resistor-1.sym
+{
+T 72600 32400 5 10 1 1 180 6 1
+refdes=R13
+T 72900 32400 5 10 1 1 180 6 1
+value=NONE
+T 73400 32000 5 10 0 1 0 6 1
+footprint=0603
+}
+C 73400 31500 1 0 1 resistor-1.sym
+{
+T 72600 31900 5 10 1 1 180 6 1
+refdes=R14
+T 73100 31900 5 10 1 1 180 6 1
+value=10K
+T 73400 31500 5 10 0 1 0 6 1
+footprint=0603
+}
+N 73400 31600 73600 31600 4
+N 73600 32300 73700 32300 4
+N 73400 32100 73600 32100 4
+C 73800 30300 1 180 0 generic-power.sym
+{
+T 73600 30050 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 73600 30300 73600 30500 4
+N 73600 31400 73600 32300 4
+C 74000 43600 1 270 0 generic-power.sym
+{
+T 74250 43400 5 10 1 1 270 3 1
+net=AGND:1
+}
+N 85200 44900 85500 44900 4
+C 85800 44800 1 90 0 gnd-1.sym
+N 83800 44900 83500 44900 4
+C 83200 45000 1 270 0 gnd-1.sym
+N 85200 37700 85500 37700 4
+C 85800 37600 1 90 0 gnd-1.sym
+N 83800 37700 83500 37700 4
+C 83200 37800 1 270 0 gnd-1.sym
+C 78200 43900 1 270 0 lm2940imp.sym
+{
+T 78200 42700 5 10 1 1 0 6 1
+refdes=U3
+}
+C 79100 41200 1 180 0 generic-power.sym
+{
+T 78900 40950 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 78700 41800 78700 41600 4
+N 79100 41600 79100 41800 4
+N 78900 41200 78900 41600 4
+C 77700 44200 1 0 0 generic-power.sym
+{
+T 77900 44450 5 10 1 1 0 3 1
+net=6V:1
+}
+N 77900 43500 77900 44200 4
+C 80000 44200 1 0 0 generic-power.sym
+{
+T 80200 44450 5 10 1 1 180 5 1
+net=5V_RF:1
+}
+N 80200 43200 80200 44200 4
+C 80400 43200 1 90 1 capacitor-2.sym
+{
+T 80700 42400 5 10 1 1 0 6 1
+refdes=C82
+T 80800 42900 5 10 1 1 0 6 1
+value=22uF
+T 80400 43200 5 10 0 1 180 2 1
+footprint=EIA6032
+}
+N 80200 41600 80200 42300 4
+N 79100 43800 79100 44000 4
+N 79100 44000 80200 44000 4
+N 77900 44000 78700 44000 4
+N 78700 44000 78700 43800 4
+C 77700 42600 1 270 1 capacitor-1.sym
+{
+T 77500 43200 5 10 1 1 0 0 1
+refdes=C83
+T 77500 42800 5 10 1 1 0 0 1
+value=.1uF
+T 77700 42600 5 10 0 1 0 2 1
+footprint=0603
+}
+N 77900 42600 77900 41600 4
+N 77900 41600 80200 41600 4
+C 76200 40300 1 180 1 capacitor-2.sym
+{
+T 76800 40200 5 10 1 1 180 8 1
+refdes=C102
+T 76600 40200 5 10 1 1 0 6 1
+value=4.7uF
+T 76200 40300 5 10 0 1 270 2 1
+footprint=1206
+}
+C 76200 40300 1 0 0 capacitor-1.sym
+{
+T 77200 40600 5 10 1 1 0 6 1
+refdes=C101
+T 76500 40600 5 10 1 1 0 6 1
+value=470pF
+T 76200 40300 5 10 0 1 90 0 1
+footprint=0603
+}
+C 76200 39500 1 180 1 capacitor-2.sym
+{
+T 76800 39400 5 10 1 1 180 8 1
+refdes=C104
+T 76600 39400 5 10 1 1 0 6 1
+value=4.7uF
+T 76200 39500 5 10 0 1 270 2 1
+footprint=1206
+}
+C 76200 39500 1 0 0 capacitor-1.sym
+{
+T 77300 39800 5 10 1 1 0 6 1
+refdes=C103
+T 76500 39800 5 10 1 1 0 6 1
+value=470pF
+T 76200 39500 5 10 0 1 90 0 1
+footprint=0603
+}
+C 76200 38700 1 180 1 capacitor-2.sym
+{
+T 76800 38600 5 10 1 1 180 8 1
+refdes=C106
+T 76600 38600 5 10 1 1 0 6 1
+value=4.7uF
+T 76200 38700 5 10 0 1 270 2 1
+footprint=1206
+}
+C 76200 38700 1 0 0 capacitor-1.sym
+{
+T 77200 39000 5 10 1 1 0 6 1
+refdes=C105
+T 76500 39000 5 10 1 1 0 6 1
+value=470pF
+T 76200 38700 5 10 0 1 90 0 1
+footprint=0603
+}
+C 76200 37900 1 180 1 capacitor-2.sym
+{
+T 76800 37800 5 10 1 1 180 8 1
+refdes=C108
+T 76600 37800 5 10 1 1 0 6 1
+value=4.7uF
+T 76200 37900 5 10 0 1 270 2 1
+footprint=1206
+}
+C 76200 37900 1 0 0 capacitor-1.sym
+{
+T 77200 38200 5 10 1 1 0 6 1
+refdes=C107
+T 76500 38200 5 10 1 1 0 6 1
+value=470pF
+T 76200 37900 5 10 0 1 90 0 1
+footprint=0603
+}
+N 76200 40500 75600 40500 4
+N 76200 40100 75600 40100 4
+N 76200 39700 75600 39700 4
+N 76200 39300 75600 39300 4
+N 76200 38900 75600 38900 4
+N 76200 38500 75600 38500 4
+N 76200 38100 75600 38100 4
+N 76200 37700 75600 37700 4
+C 77600 37500 1 180 0 generic-power.sym
+{
+T 77400 37250 5 10 1 1 180 3 1
+net=AGND:1
+}
+N 77400 37500 77400 40500 4
+N 77400 40500 77100 40500 4
+N 77400 40100 77100 40100 4
+N 77400 39300 77100 39300 4
+N 77400 39700 77100 39700 4
+N 77400 37700 77100 37700 4
+N 77400 38100 77100 38100 4
+N 77400 38500 77100 38500 4
+N 77400 38900 77100 38900 4
diff --git a/usrp-hw/usrp/ChangeLog b/usrp-hw/usrp/ChangeLog
new file mode 100644
index 000000000..36856e6be
--- /dev/null
+++ b/usrp-hw/usrp/ChangeLog
@@ -0,0 +1,79 @@
+2004-11-22  Matt Ettus <matt@ettus.com>
+
+	* fpga.sch : 
+		- Added R2001-R2005.  
+		- Jumpers to gnd for TXBLANK.
+		- Unpopulated resistors for redoing SPI, shared with io_tx_a/b[15]
+
+2004-11-03  Matt Ettus <matt@ettus.com>
+
+	* fpga.sch : Removed J900 and J902 which were to test the FX2 bus.  
+		The lines were just too long.
+
+2004-10-27  Matt Ettus <matt@ettus.com>
+
+	* power.sch : Removed text note
+
+	* dboard.sch : Swapped RS-232 so that each board gets a pair, shared between RX and TX
+	
+	* interface.sch : 
+		- Removed U410 (MAX232) and associated caps
+		- Rerouted RS232 signals so they go out as CMOS levels
+		- Removed J645 which was PE[2:0]
+
+	* fpga.sch :
+		- Redid FX2 bus interface probe pins on J900
+		- Added J902 with FX2 data bus
+		
+2004-10-23  Matt Ettus <matt@ettus.com>
+
+	* netlist_cmd :
+		- Added command script for generating a netlist
+	* power.sch :
+		- Added J1001 for ground testpoints
+		- Added C0603 footprint to a bunch of caps.  
+
+2004-10-10  Matt Ettus <matt@ettus.com>
+
+	* fpga.sch :
+		- Remove io_tx_b_15 from VCXO tuning, remove R800,R803,R876,C800,C804
+		- Connect X2.1 to DVDD
+		- Removed nets CLKOUT1_x and CLKOUT2_x
+		- Removed R801, R802, R857 -- CLK120 now goes straight to FPGA
+		- Removed J901
+		- Split CLK120 into CLK_FPGA, CLK_CODEC_A, and CLK_CODEC_B, each with proper source and sink terminations.  Use 50 ohm lines.
+		- Added R1011-R1016 and C1014-C1016 for terminations
+		- Added MYSTERY_SIGNAL to replace one RX_SYNC
+		- Moved SDO to where TX_BLANK was
+		- Moved SDI to one RX_SYNC
+		- Moved SEN_FPGA to where RESET was
+
+	* dboard.sch :
+		- Removed CLKOUT1_x and CLKOUT2_x
+		- Removed io_[tx,rx]_x_16 which never did anything
+
+	* interface.sch :
+		- Added MYSTERY_SIGNAL input to INT4
+
+	* power.sch :
+		- Removed D501
+		- Added C1020 for more decoupling of 5V
+		- Increased value of C502 to 100 uF
+
+2004-10-08  Matt Ettus  <matt@ettus.com>
+
+	* interface.sch :
+		- Reset on PC0 is now RESET_CODEC
+		- Tool changed format of Text items
+		- NB -  Need to find pin for RESET_FPGA.  Maybe PE0,1,2 or FX2_1.  Send rest to dboard?
+
+	* dboard.sch :
+		- R701, R702 changed from 2K to 4K, to fit what the datasheet tells us.
+		- R1001,R1002,R1003,R1004,C1001,C1002,C1003,C1004 added to do sigma delta filtering on the motherboard
+		- Net SIGDEL_x no longer goes to dboard.  It gets filtered, and AUX_DAC_D_x is sent
+		- RESET on CODECs and Dboards is now RESET_CODEC
+		- Tool changed format of Text items
+		- NB -  Should we avoid sending REFIO_x to the dboards for sig integrity?
+		- NB -  Get rid of io_tx/rx_x_16
+		- NB -  Find a bit 15 for io buses
+
diff --git a/usrp-hw/usrp/dboard.sch b/usrp-hw/usrp/dboard.sch
new file mode 100644
index 000000000..3a6a9bc94
--- /dev/null
+++ b/usrp-hw/usrp/dboard.sch
@@ -0,0 +1,1604 @@
+v 20040111 1
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+{
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+}
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+{
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+}
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+{
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+}
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+{
+T 92300 36900 5 10 1 1 90 2 1
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+}
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+}
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+{
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+}
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+T 78600 46800 5 10 1 1 0 6 1
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+}
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+}
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diff --git a/usrp-hw/usrp/fpga.sch b/usrp-hw/usrp/fpga.sch
new file mode 100644
index 000000000..745da5029
--- /dev/null
+++ b/usrp-hw/usrp/fpga.sch
@@ -0,0 +1,1887 @@
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+T 81300 22600 8 14 1 1 0 4 1
+title=USRP FPGA and CODECs
+T 78900 21600 9 10 1 0 0 0 1
+3
+T 79700 21600 9 10 1 0 0 0 1
+4
+N 51700 49600 53400 49600 4
+{
+T 51700 49600 5 10 1 1 0 0 1
+netname=MYSTERY_SIGNAL
+}
+N 70700 29500 70700 31100 4
+{
+T 70700 30700 5 10 1 1 270 0 1
+netname=SDI
+}
+N 66000 26600 66000 28400 4
+{
+T 66000 28100 5 10 1 1 270 0 1
+netname=GPIF_RDY2
+}
+N 65600 26600 65600 28400 4
+{
+T 65600 28100 5 10 1 1 270 0 1
+netname=GPIF_RDY3
+}
+N 65200 26600 65200 28400 4
+{
+T 65200 28100 5 10 1 1 270 0 1
+netname=GPIF_RDY4
+}
+N 64800 26600 64800 28400 4
+{
+T 64800 28100 5 10 1 1 270 0 1
+netname=GPIF_RDY5
+}
+N 68000 26600 68000 28400 4
+{
+T 68000 28100 5 10 1 1 270 0 1
+netname=GPIF_CTL3
+}
+N 67600 26600 67600 28400 4
+{
+T 67600 28100 5 10 1 1 270 0 1
+netname=GPIF_CTL4
+}
+N 67200 26600 67200 28400 4
+{
+T 67200 28100 5 10 1 1 270 0 1
+netname=GPIF_CTL5
+}
+N 60500 41000 61700 41000 4
+{
+T 61700 41000 5 10 1 1 0 6 1
+netname=CLK_FPGA
+}
+C 68600 40200 1 270 1 resistor-1.sym
+{
+T 68900 40700 5 10 1 1 0 2 1
+refdes=R858
+T 68600 40200 5 10 0 1 90 2 1
+footprint=0603
+T 68900 40400 5 10 1 1 0 0 1
+value=NONE
+}
+C 68800 39800 1 0 1 gnd-1.sym
+C 68900 42300 1 0 1 generic-power.sym
+{
+T 68700 42550 5 10 1 1 0 3 1
+net=DVDD:1
+}
+C 68600 41300 1 270 1 resistor-1.sym
+{
+T 68900 41900 5 10 1 1 0 2 1
+refdes=R859
+T 68600 41300 5 10 0 1 90 2 1
+footprint=0603
+T 68900 41600 5 10 1 1 0 0 1
+value=0
+}
+N 68700 40100 68700 40200 4
+N 68700 41100 68700 41300 4
+N 67100 41200 68700 41200 4
+N 68700 42200 68700 42300 4
+C 68800 36200 1 90 0 resistor-1.sym
+{
+T 68900 36600 5 10 1 1 0 0 1
+refdes=R860
+T 68800 36200 5 10 0 1 90 0 1
+footprint=0603
+T 68900 36400 5 10 1 1 0 0 1
+value=NONE
+}
+C 68600 35800 1 0 0 gnd-1.sym
+C 68500 38300 1 0 0 generic-power.sym
+{
+T 68700 38550 5 10 1 1 0 3 1
+net=DVDD:1
+}
+C 68800 37300 1 90 0 resistor-1.sym
+{
+T 68900 37700 5 10 1 1 0 0 1
+refdes=R861
+T 68800 37300 5 10 0 1 90 0 1
+footprint=0603
+T 68900 37500 5 10 1 1 0 0 1
+value=0
+}
+N 68700 36100 68700 36200 4
+N 68700 37100 68700 37300 4
+N 68700 38200 68700 38300 4
+C 62400 47900 1 270 0 generic-power.sym
+{
+T 62650 47700 5 10 1 1 270 3 1
+net=DVDD:1
+}
+N 62200 47700 62400 47700 4
+N 67100 37200 68700 37200 4
+C 64800 48000 1 0 1 resistor-1.sym
+{
+T 64600 48300 5 10 1 1 180 2 1
+refdes=R1011
+T 64800 48000 5 10 0 1 180 2 1
+footprint=0603
+T 64200 47800 5 10 1 1 0 0 1
+value=50
+}
+C 64800 47200 1 0 1 resistor-1.sym
+{
+T 64600 47500 5 10 1 1 180 2 1
+refdes=R1012
+T 64800 47200 5 10 0 1 180 2 1
+footprint=0603
+T 64200 47000 5 10 1 1 0 0 1
+value=50
+}
+C 64800 46400 1 0 1 resistor-1.sym
+{
+T 64600 46700 5 10 1 1 180 2 1
+refdes=R1013
+T 64800 46400 5 10 0 1 180 2 1
+footprint=0603
+T 64200 46200 5 10 1 1 0 0 1
+value=50
+}
+N 63200 48100 63200 46500 4
+N 63900 47300 63200 47300 4
+C 65100 45100 1 270 0 capacitor-1.sym
+{
+T 65400 44300 5 10 1 1 0 0 1
+refdes=C1014
+T 65400 44100 5 10 1 1 0 0 1
+value=220pF
+T 65100 45100 5 10 0 1 0 0 1
+footprint=0603
+}
+C 65400 43700 1 0 1 gnd-1.sym
+C 65200 45300 1 270 1 resistor-1.sym
+{
+T 66000 45900 5 10 1 1 180 2 1
+refdes=R1014
+T 65200 45300 5 10 0 1 90 2 1
+footprint=0603
+T 65500 45700 5 10 1 1 0 0 1
+value=50
+}
+N 65300 44000 65300 44200 4
+N 65300 45100 65300 45300 4
+C 66000 45100 1 270 0 capacitor-1.sym
+{
+T 66300 44300 5 10 1 1 0 0 1
+refdes=C1015
+T 66300 44100 5 10 1 1 0 0 1
+value=220pF
+T 66000 45100 5 10 0 1 0 0 1
+footprint=0603
+}
+C 66300 43700 1 0 1 gnd-1.sym
+C 66100 45300 1 270 1 resistor-1.sym
+{
+T 66900 45900 5 10 1 1 180 2 1
+refdes=R1015
+T 66100 45300 5 10 0 1 90 2 1
+footprint=0603
+T 66400 45700 5 10 1 1 0 0 1
+value=50
+}
+N 66200 44000 66200 44200 4
+N 66200 45100 66200 45300 4
+C 66900 45100 1 270 0 capacitor-1.sym
+{
+T 67200 44300 5 10 1 1 0 0 1
+refdes=C1016
+T 67200 44100 5 10 1 1 0 0 1
+value=220pF
+T 66900 45100 5 10 0 1 0 0 1
+footprint=0603
+}
+C 67200 43700 1 0 1 gnd-1.sym
+C 67000 45300 1 270 1 resistor-1.sym
+{
+T 67800 45900 5 10 1 1 180 2 1
+refdes=R1016
+T 67000 45300 5 10 0 1 90 2 1
+footprint=0603
+T 67300 45700 5 10 1 1 0 0 1
+value=50
+}
+N 67100 44000 67100 44200 4
+N 67100 45100 67100 45300 4
+N 64800 46500 65300 46500 4
+{
+T 65000 46500 5 10 1 1 0 0 1
+netname=CLK_CODEC_B
+}
+N 65300 46200 65300 46500 4
+N 66200 46200 66200 47300 4
+N 66200 47300 64800 47300 4
+{
+T 64900 47300 5 10 1 1 0 0 1
+netname=CLK_CODEC_A
+}
+N 64800 48100 67100 48100 4
+{
+T 64900 48100 5 10 1 1 0 0 1
+netname=CLK_FPGA
+}
+N 67100 48100 67100 46200 4
+C 68800 54600 1 0 0 resistor-1.sym
+{
+T 69600 55000 5 10 1 1 180 0 1
+refdes=R2001
+T 68800 54600 5 10 0 1 180 8 1
+footprint=0603
+T 69200 54900 5 10 1 1 180 2 1
+value=NONE
+}
+C 76600 43100 1 270 1 resistor-1.sym
+{
+T 76900 43700 5 10 1 1 0 2 1
+refdes=R2002
+T 76600 43100 5 10 0 1 90 2 1
+footprint=0603
+T 76900 43400 5 10 1 1 0 0 1
+value=0
+}
+C 51000 37000 1 270 1 resistor-1.sym
+{
+T 51300 37600 5 10 1 1 0 2 1
+refdes=R2003
+T 51000 37000 5 10 0 1 90 2 1
+footprint=0603
+T 51300 37300 5 10 1 1 0 0 1
+value=0
+}
+C 51000 36400 1 0 0 gnd-1.sym
+N 51100 36700 51100 37000 4
+N 48700 38300 51100 38300 4
+{
+T 49900 38300 5 10 1 1 180 0 1
+netname=TXBLANK_B
+}
+N 51100 38300 51100 37900 4
+C 76600 42600 1 0 0 gnd-1.sym
+N 76700 42900 76700 43100 4
+N 76700 44000 76700 44300 4
+C 53200 50000 1 0 1 resistor-1.sym
+{
+T 52700 50300 5 10 1 1 90 2 1
+refdes=R2004
+T 53200 50000 5 10 0 1 180 2 1
+footprint=0603
+T 53000 50300 5 10 1 1 90 0 1
+value=NONE
+}
+N 53200 50100 53400 50100 4
+N 53400 50100 53400 49600 4
+N 60100 38600 61700 38600 4
+{
+T 60500 38600 5 10 1 1 0 0 1
+netname=SCLK
+}
+N 69700 54700 71300 54700 4
+{
+T 71200 54700 5 10 1 1 0 6 1
+netname=SEN_CODEC_A
+}
+C 51200 40400 1 270 1 resistor-1.sym
+{
+T 51500 40900 5 10 1 1 0 2 1
+refdes=R2005
+T 51200 40400 5 10 0 1 90 2 1
+footprint=0603
+T 51500 40600 5 10 1 1 0 0 1
+value=NONE
+}
+N 51300 40400 51300 38800 4
+{
+T 51300 38900 5 10 1 1 90 0 1
+netname=SEN_CODEC_B
+}
+N 51300 41300 51300 41600 4
+N 51300 41600 53400 41600 4
+{
+T 52200 41600 5 10 1 1 0 0 1
+netname=io_tx_b_15
+}
+N 68300 52100 68300 54700 4
+{
+T 68300 52900 5 10 1 1 90 0 1
+netname=io_tx_a_15
+}
+N 68300 54700 68800 54700 4
+C 61100 46000 1 0 0 SMA-5.sym
+{
+T 61100 46800 5 10 1 1 0 0 1
+refdes=J2001
+T 61100 46000 5 10 0 1 0 6 1
+footprint=SMA_VERT
+}
+C 62900 46400 1 0 1 resistor-1.sym
+{
+T 62700 46700 5 10 1 1 180 2 1
+refdes=R2027
+T 62900 46400 5 10 0 1 180 2 1
+footprint=0603
+T 62300 46200 5 10 1 1 0 0 1
+value=50
+}
+N 61600 46500 62000 46500 4
+N 62900 46500 63900 46500 4
+C 61300 45500 1 0 1 gnd-1.sym
+N 61200 45800 61200 46000 4
diff --git a/usrp-hw/usrp/gnetlistrc b/usrp-hw/usrp/gnetlistrc
new file mode 100644
index 000000000..6bbd9c292
--- /dev/null
+++ b/usrp-hw/usrp/gnetlistrc
@@ -0,0 +1,3 @@
+(component-library "../sym")
+(component-library "../sym/generated")
+
diff --git a/usrp-hw/usrp/gschemrc b/usrp-hw/usrp/gschemrc
new file mode 100644
index 000000000..6bbd9c292
--- /dev/null
+++ b/usrp-hw/usrp/gschemrc
@@ -0,0 +1,3 @@
+(component-library "../sym")
+(component-library "../sym/generated")
+
diff --git a/usrp-hw/usrp/interface.sch b/usrp-hw/usrp/interface.sch
new file mode 100644
index 000000000..f5b72f8a1
--- /dev/null
+++ b/usrp-hw/usrp/interface.sch
@@ -0,0 +1,450 @@
+v 20040111 1
+C 17200 44300 1 0 0 cy7c68013-tq100-CTRL.sym
+{
+T 68200 74600 5 10 1 1 0 6 1
+refdes=U412
+}
+C 114700 36300 1 0 1 cy7c68013-tq100-MISC.sym
+{
+T 63800 66600 5 10 1 1 0 0 1
+refdes=U412
+}
+C 16300 92600 1 180 1 cy7c68013-tq100-PC.sym
+{
+T 67100 66400 5 10 1 1 180 0 1
+refdes=U412
+}
+C 21600 93000 1 180 1 ep1c12-pq240-CFG.sym
+{
+T 72500 67200 5 10 1 1 180 0 1
+refdes=U101
+}
+C 7000 97300 1 180 1 ep1c12-pq240-JTAG.sym
+{
+T 57800 69500 5 10 1 1 180 0 1
+refdes=U101
+}
+C 59500 65900 1 0 0 24Cxx-1.sym
+{
+T 60000 67100 5 10 1 1 0 0 1
+refdes=U413
+T 59500 65900 5 10 0 1 0 0 1
+footprint=SO8
+T 59800 65700 5 10 1 1 0 0 1
+device=24LC02B
+T 59800 65300 5 10 1 1 0 0 1
+net=GND:4
+T 59800 65500 5 10 1 1 0 0 1
+net=DVDD:8
+}
+C 70800 66000 1 90 0 generic-power.sym
+{
+T 70550 66200 5 10 1 1 90 3 1
+net=DVDD:1
+}
+C 70600 65900 1 270 0 gnd-1.sym
+N 71300 65800 70900 65800 4
+N 70800 66200 71300 66200 4
+C 70600 66700 1 270 0 gnd-1.sym
+N 71300 66600 70900 66600 4
+N 68000 65000 71300 65000 4
+N 68000 64600 71300 64600 4
+N 68000 64200 71300 64200 4
+N 71300 63800 68000 63800 4
+N 71300 63400 68000 63400 4
+C 68800 69900 1 0 0 generic-power.sym
+{
+T 69000 70150 5 10 1 1 0 3 1
+net=DVDD:1
+}
+C 68000 68100 1 270 0 led-1.sym
+{
+T 67600 67300 5 10 1 1 0 0 1
+refdes=D402
+}
+C 68600 67500 1 270 0 led-1.sym
+{
+T 68200 66700 5 10 1 1 0 0 1
+refdes=D403
+}
+C 70200 67300 1 90 0 resistor-1.sym
+{
+T 70500 67700 5 10 1 1 180 0 1
+value=10K
+T 70200 67300 5 10 0 1 90 0 1
+footprint=0603
+T 70200 67300 5 10 1 1 0 0 1
+refdes=R101
+}
+C 69900 66700 1 90 0 resistor-1.sym
+{
+T 70200 67100 5 10 1 1 180 0 1
+value=10K
+T 69900 66700 5 10 0 1 90 0 1
+footprint=0603
+T 69900 66700 5 10 1 1 0 0 1
+refdes=R102
+}
+C 69600 67000 1 90 0 resistor-1.sym
+{
+T 69300 67600 5 10 1 1 180 0 1
+value=10K
+T 69600 67000 5 10 0 1 90 0 1
+footprint=0603
+T 69100 67200 5 10 1 1 0 0 1
+refdes=R104
+}
+C 68900 67700 1 90 0 resistor-1.sym
+{
+T 69200 68100 5 10 1 1 180 0 1
+value=1K
+T 68900 67700 5 10 0 1 90 0 1
+footprint=0603
+T 68900 67700 5 10 1 1 0 0 1
+refdes=R420
+}
+C 68300 68300 1 90 0 resistor-1.sym
+{
+T 68600 68700 5 10 1 1 180 0 1
+value=1K
+T 68300 68300 5 10 0 1 90 0 1
+footprint=0603
+T 68300 68300 5 10 1 1 0 0 1
+refdes=R422
+}
+N 68200 67200 68200 65800 4
+N 68200 65800 68000 65800 4
+N 68800 66600 68800 65400 4
+N 68800 65400 68000 65400 4
+N 68200 68100 68200 68300 4
+N 68200 69200 68200 69500 4
+N 68800 69500 68800 68600 4
+N 68800 67500 68800 67700 4
+N 69500 69500 69500 67900 4
+N 69800 69500 69800 67600 4
+N 70100 68200 70100 69500 4
+N 68200 69500 70100 69500 4
+N 69000 69900 69000 69500 4
+N 69500 67000 69500 65000 4
+N 69800 66700 69800 64600 4
+N 70100 67300 70100 63800 4
+C 64200 74000 1 180 1 connector4-1.sym
+{
+T 64200 72600 5 10 1 1 180 6 1
+refdes=J401
+T 64200 74000 5 10 0 1 0 0 1
+footprint=USB
+}
+N 65900 73500 66900 73500 4
+C 66600 73700 1 90 0 gnd-1.sym
+N 65900 73800 66300 73800 4
+C 65700 71800 1 0 0 crystal-1.sym
+{
+T 65900 72100 5 10 1 1 0 0 1
+refdes=X1
+T 65700 71800 5 10 0 1 0 0 1
+footprint=HC-49USMD
+}
+C 65300 71700 1 270 0 capacitor-1.sym
+{
+T 65000 70900 5 10 1 1 0 0 1
+refdes=C460
+T 65000 70700 5 10 1 1 0 0 1
+value=22pF
+T 65300 71700 5 10 0 1 0 0 1
+footprint=0603
+}
+C 66400 71700 1 270 0 capacitor-1.sym
+{
+T 66100 70900 5 10 1 1 0 0 1
+refdes=C464
+T 66100 70700 5 10 1 1 0 0 1
+value=22pF
+T 66400 71700 5 10 0 1 0 0 1
+footprint=0603
+}
+C 66000 70200 1 0 0 gnd-1.sym
+N 65500 70800 65500 70600 4
+N 65500 70600 66600 70600 4
+N 66600 70600 66600 70800 4
+N 66100 70500 66100 70600 4
+N 65500 71900 65700 71900 4
+N 66400 71900 66600 71900 4
+N 66600 71700 66600 72300 4
+N 66600 72300 66900 72300 4
+N 66900 72700 65500 72700 4
+N 65500 71700 65500 72700 4
+C 69700 73000 1 90 0 gnd-1.sym
+N 68900 73100 69400 73100 4
+C 70200 72600 1 270 0 capacitor-1.sym
+{
+T 69900 71800 5 10 1 1 0 0 1
+refdes=C470
+T 69900 71600 5 10 1 1 0 0 1
+value=0.1uF
+T 70200 72600 5 10 0 1 0 0 1
+footprint=0603
+}
+C 70500 72800 1 90 0 resistor-1.sym
+{
+T 71000 73200 5 10 1 1 180 0 1
+value=100K
+T 70500 72800 5 10 0 1 90 0 1
+footprint=0603
+T 70600 73300 5 10 1 1 0 0 1
+refdes=R424
+}
+N 68900 72700 70400 72700 4
+N 70400 72600 70400 72800 4
+C 70300 71200 1 0 0 gnd-1.sym
+N 70400 71500 70400 71700 4
+C 70200 73900 1 0 0 generic-power.sym
+{
+T 70400 74150 5 10 1 1 0 3 1
+net=DVDD:1
+}
+N 70400 73700 70400 73900 4
+C 56400 69000 1 180 0 resistor-1.sym
+{
+T 56300 69200 5 10 1 1 180 0 1
+value=10K
+T 56400 69000 5 10 0 1 180 0 1
+footprint=0603
+T 55800 69200 5 10 1 1 180 0 1
+refdes=R490
+}
+C 55000 69100 1 0 0 generic-power.sym
+{
+T 55200 69350 5 10 1 1 0 3 1
+net=DVDD:1
+}
+C 56400 68200 1 180 0 resistor-1.sym
+{
+T 56000 68300 5 10 1 1 0 0 1
+value=10K
+T 56400 68200 5 10 0 1 180 0 1
+footprint=0603
+T 55800 68400 5 10 1 1 180 0 1
+refdes=R491
+}
+C 55100 67200 1 0 0 gnd-1.sym
+C 56400 67800 1 180 0 resistor-1.sym
+{
+T 56000 67800 5 10 1 1 0 0 1
+value=10K
+T 56400 67800 5 10 0 1 180 0 1
+footprint=0603
+T 55300 67800 5 10 1 1 0 0 1
+refdes=R492
+}
+N 56400 68900 56700 68900 4
+N 56400 68100 56700 68100 4
+N 56400 67700 56700 67700 4
+N 55200 67500 55200 67700 4
+N 55200 67700 55500 67700 4
+N 55200 69100 55200 68100 4
+N 55200 68100 55500 68100 4
+N 55200 68900 55500 68900 4
+N 60800 66200 62200 66200 4
+{
+T 61700 66200 5 10 1 1 0 0 1
+netname=SCL
+}
+N 62200 66200 62200 65900 4
+N 62200 65900 63000 65900 4
+N 60800 66000 62000 66000 4
+{
+T 61600 66000 5 10 1 1 0 0 1
+netname=SDA
+}
+N 62000 66000 62000 65500 4
+N 62000 65500 63000 65500 4
+C 61800 66500 1 180 0 resistor-1.sym
+{
+T 61700 66500 5 10 1 1 0 0 1
+value=0
+T 61800 66500 5 10 0 1 180 0 1
+footprint=0603
+T 60800 66500 5 10 1 1 0 0 1
+refdes=R442
+}
+N 60800 66400 60900 66400 4
+C 62200 66300 1 90 0 gnd-1.sym
+N 61800 66400 61900 66400 4
+C 59200 65800 1 0 0 gnd-1.sym
+N 59300 66100 59300 66600 4
+N 59300 66600 59500 66600 4
+N 59300 66400 59500 66400 4
+N 59300 66200 59500 66200 4
+C 62300 68500 1 0 0 generic-power.sym
+{
+T 62500 68750 5 10 1 1 0 3 1
+net=DVDD:1
+}
+C 62700 67900 1 270 0 resistor-1.sym
+{
+T 63300 67900 5 10 1 1 180 0 1
+value=2.2K
+T 62700 67900 5 10 0 1 270 0 1
+footprint=0603
+T 63300 67500 5 10 1 1 180 0 1
+refdes=R417
+}
+C 62400 67900 1 270 0 resistor-1.sym
+{
+T 62400 67900 5 10 1 1 180 0 1
+value=2.2K
+T 62400 67900 5 10 0 1 270 0 1
+footprint=0603
+T 62300 67500 5 10 1 1 180 0 1
+refdes=R418
+}
+N 62500 68100 62800 68100 4
+N 62800 68100 62800 67900 4
+N 62500 67900 62500 68500 4
+N 62800 67000 62800 65900 4
+N 62500 67000 62500 65500 4
+N 61300 65100 63000 65100 4
+{
+T 61600 65100 5 10 1 1 0 0 1
+netname=RS232_TXD_1
+}
+N 61300 64700 63000 64700 4
+{
+T 61600 64700 5 10 1 1 0 0 1
+netname=RS232_RXD_1
+}
+N 61300 64300 63000 64300 4
+{
+T 61600 64300 5 10 1 1 0 0 1
+netname=RS232_TXD_2
+}
+N 61300 63900 63000 63900 4
+{
+T 61600 63900 5 10 1 1 0 0 1
+netname=RS232_RXD_2
+}
+N 65900 73200 66400 73200 4
+N 66400 73200 66400 73100 4
+N 66400 73100 66900 73100 4
+N 70100 63000 68000 63000 4
+{
+T 68400 63000 5 10 1 1 0 0 1
+netname=RESET_CODEC
+}
+C 10500 44100 1 0 0 cy7c68013-tq100-PA.sym
+{
+T 61500 74400 5 10 1 1 180 2 1
+refdes=U412
+}
+N 62200 73700 63200 73700 4
+{
+T 63100 73700 5 10 1 1 0 6 1
+netname=SCLK
+}
+N 62200 72900 63200 72900 4
+{
+T 63000 72900 5 10 1 1 0 6 1
+netname=SDO
+}
+N 58100 71300 59300 71300 4
+{
+T 58200 71300 5 10 1 1 0 0 1
+netname=SEN_TX_B
+}
+N 62200 73300 63200 73300 4
+{
+T 62900 73300 5 10 1 1 0 6 1
+netname=SDI
+}
+N 58100 70900 59300 70900 4
+{
+T 58200 70900 5 10 1 1 0 0 1
+netname=SEN_RX_B
+}
+N 62200 71700 63900 71700 4
+{
+T 62300 71700 5 10 1 1 0 0 1
+netname=SEN_CODEC_B
+}
+N 62200 72100 63900 72100 4
+{
+T 62300 72100 5 10 1 1 0 0 1
+netname=SEN_CODEC_A
+}
+C 6400 44100 1 0 0 cy7c68013-tq100-PE.sym
+{
+T 57300 74400 5 10 1 1 0 6 1
+refdes=U412
+}
+N 58100 72100 59300 72100 4
+{
+T 58200 72100 5 10 1 1 0 0 1
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diff --git a/usrp-hw/usrp/netlist_cmd b/usrp-hw/usrp/netlist_cmd
new file mode 100755
index 000000000..234de1238
--- /dev/null
+++ b/usrp-hw/usrp/netlist_cmd
@@ -0,0 +1,3 @@
+gnetlist -g pads -o usrp_mboard.net power.sch fpga.sch interface.sch  dboard.sch
+gnetlist -g partslist3 -o usrp_mboard.bom power.sch fpga.sch interface.sch  dboard.sch
+
diff --git a/usrp-hw/usrp/power.sch b/usrp-hw/usrp/power.sch
new file mode 100644
index 000000000..57cebf365
--- /dev/null
+++ b/usrp-hw/usrp/power.sch
@@ -0,0 +1,1983 @@
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