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author | jcorgan | 2009-01-05 18:05:17 +0000 |
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committer | jcorgan | 2009-01-05 18:05:17 +0000 |
commit | 54625297142c1ed5ac4665d48ae6dea997b7b7eb (patch) | |
tree | 0a5cf4125c20e4a4597b0d4748e375b5c8beba1b | |
parent | b54ab8fc36e242e0ae9c0fad99e1eda5d6423bd1 (diff) | |
download | gnuradio-54625297142c1ed5ac4665d48ae6dea997b7b7eb.tar.gz gnuradio-54625297142c1ed5ac4665d48ae6dea997b7b7eb.tar.bz2 gnuradio-54625297142c1ed5ac4665d48ae6dea997b7b7eb.zip |
Allow setting of non-standard FPGA master clock frequency for USRP1
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10193 221aa14e-8319-0410-a670-987f0aec2ac5
-rw-r--r-- | gr-usrp/src/usrp_base.cc | 6 | ||||
-rw-r--r-- | gr-usrp/src/usrp_base.h | 11 | ||||
-rw-r--r-- | gr-usrp/src/usrp_base.i | 3 | ||||
-rw-r--r-- | usrp/host/lib/legacy/usrp_basic.cc | 2 | ||||
-rw-r--r-- | usrp/host/lib/legacy/usrp_basic.h | 13 |
5 files changed, 30 insertions, 5 deletions
diff --git a/gr-usrp/src/usrp_base.cc b/gr-usrp/src/usrp_base.cc index 1709c7a44..a4cf64ed7 100644 --- a/gr-usrp/src/usrp_base.cc +++ b/gr-usrp/src/usrp_base.cc @@ -83,6 +83,12 @@ usrp_base::fpga_master_clock_freq() const } void +usrp_base::set_fpga_master_clock_freq(long master_clock) +{ + d_usrp_basic->set_fpga_master_clock_freq(master_clock); +} + +void usrp_base::set_verbose (bool verbose) { d_usrp_basic->set_verbose (verbose); diff --git a/gr-usrp/src/usrp_base.h b/gr-usrp/src/usrp_base.h index 83aa699ab..c106739d0 100644 --- a/gr-usrp/src/usrp_base.h +++ b/gr-usrp/src/usrp_base.h @@ -98,7 +98,16 @@ public: /*! * \brief return frequency of master oscillator on USRP */ - long fpga_master_clock_freq() const; + long fpga_master_clock_freq() const; + + /*! + * Tell API that the master oscillator on the USRP is operating at a non-standard + * fixed frequency. This is only needed for custom USRP hardware modified to + * operate at a different frequency from the default factory configuration. This + * function must be called prior to any other API function. + * \param master_clock USRP2 FPGA master clock frequency in Hz (10..64 MHz) + */ + void set_fpga_master_clock_freq (long master_clock); void set_verbose (bool on); diff --git a/gr-usrp/src/usrp_base.i b/gr-usrp/src/usrp_base.i index 8f0c8368d..d0ece1fb2 100644 --- a/gr-usrp/src/usrp_base.i +++ b/gr-usrp/src/usrp_base.i @@ -38,7 +38,8 @@ public: db_base_sptr db(int which_side, int which_dev); %rename (_real_selected_subdev) selected_subdev; db_base_sptr selected_subdev(usrp_subdev_spec ss); - long fpga_master_clock_freq() const; + long fpga_master_clock_freq() const; + void set_fpga_master_clock_freq(long master_clock); void set_verbose (bool on); static const int READ_FAILED = -99999; bool write_eeprom (int i2c_addr, int eeprom_offset, const std::string buf); diff --git a/usrp/host/lib/legacy/usrp_basic.cc b/usrp/host/lib/legacy/usrp_basic.cc index e63a097ac..883e5ede4 100644 --- a/usrp/host/lib/legacy/usrp_basic.cc +++ b/usrp/host/lib/legacy/usrp_basic.cc @@ -112,7 +112,7 @@ usrp_basic::usrp_basic (int which_board, : d_udh (0), d_usb_data_rate (16000000), // SWAG, see below d_bytes_per_poll ((int) (POLLING_INTERVAL * d_usb_data_rate)), - d_verbose (false), d_db(2) + d_verbose (false), d_fpga_master_clock_freq(64000000), d_db(2) { /* * SWAG: Scientific Wild Ass Guess. diff --git a/usrp/host/lib/legacy/usrp_basic.h b/usrp/host/lib/legacy/usrp_basic.h index c5e3d2824..2caac7b66 100644 --- a/usrp/host/lib/legacy/usrp_basic.h +++ b/usrp/host/lib/legacy/usrp_basic.h @@ -1,4 +1,3 @@ - /* -*- c++ -*- */ /* * Copyright 2003,2004,2008 Free Software Foundation, Inc. @@ -69,6 +68,7 @@ protected: int d_usb_data_rate; // bytes/sec int d_bytes_per_poll; // how often to poll for overruns bool d_verbose; + long d_fpga_master_clock_freq; static const int MAX_REGS = 128; unsigned int d_fpga_shadows[MAX_REGS]; @@ -177,7 +177,16 @@ public: /*! * \brief return frequency of master oscillator on USRP */ - long fpga_master_clock_freq () const { return 64000000; } + long fpga_master_clock_freq () const { return d_fpga_master_clock_freq; } + + /*! + * Tell API that the master oscillator on the USRP is operating at a non-standard + * fixed frequency. This is only needed for custom USRP hardware modified to + * operate at a different frequency from the default factory configuration. This + * function must be called prior to any other API function. + * \param master_clock USRP2 FPGA master clock frequency in Hz (10..64 MHz) + */ + void set_fpga_master_clock_freq (long master_clock) { d_fpga_master_clock_freq = master_clock; } /*! * \returns usb data rate in bytes/sec |