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| author | Matt Ettus | 2009-09-10 11:40:18 -0700 |
|---|---|---|
| committer | Matt Ettus | 2009-09-10 11:40:18 -0700 |
| commit | 4623a334d042b0f982ead3dcc7ea63015a39ff72 (patch) | |
| tree | c51d5329fd1a7f6df58c1ed3bf3fc411598dde18 | |
| parent | db03fafeec9d360a9837303befcc2dbcce57a06b (diff) | |
| download | gnuradio-4623a334d042b0f982ead3dcc7ea63015a39ff72.tar.gz gnuradio-4623a334d042b0f982ead3dcc7ea63015a39ff72.tar.bz2 gnuradio-4623a334d042b0f982ead3dcc7ea63015a39ff72.zip | |
might as well use a cascade fifo to help timing and give a little more capacity
| -rw-r--r-- | usrp2/fpga/simple_gemac/simple_gemac_wrapper.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/fpga/simple_gemac/simple_gemac_wrapper.v b/usrp2/fpga/simple_gemac/simple_gemac_wrapper.v index 7511f3fb9..71ad0cf0f 100644 --- a/usrp2/fpga/simple_gemac/simple_gemac_wrapper.v +++ b/usrp2/fpga/simple_gemac/simple_gemac_wrapper.v @@ -110,7 +110,7 @@ module simple_gemac_wrapper wire [35:0] tx_f36_data_int1; wire tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1; - fifo_2clock #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_2clk_fifo + fifo_2clock_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_2clk_fifo (.wclk(sys_clk), .datain(tx_f36_data), .src_rdy_i(tx_f36_src_rdy), .dst_rdy_o(tx_f36_dst_rdy), .space(), .rclk(tx_clk), .dataout(tx_f36_data_int1), |