blob: ae1c5af6b5f52245e9823e5ff6011376a60b0d9f (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_04a is
end entity inline_04a;
----------------------------------------------------------------
architecture test of inline_04a is
type gear_type is (gear_1, gear_2, neutral);
signal gear : gear_type := gear_1;
signal gear_engaged : boolean := false;
begin
process_1_d : process (gear) is
variable max_acceleration : real := 0.0;
variable reverse_indicator : boolean := true;
begin
-- code from book:
if gear = neutral then
max_acceleration := 0.0;
reverse_indicator := false;
gear_engaged <= false;
end if;
-- end of code from book
end process process_1_d;
stimulus : process is
begin
gear <= gear_2 after 100 ns, neutral after 200 ns;
wait;
end process stimulus;
end architecture test;
|
