1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package bus_monitor_pkg is
type stats_type is record
ifetch_freq, write_freq, read_freq : real;
end record stats_type;
component bus_monitor is
generic ( verbose, dump_stats : boolean := false );
port ( mem_req, ifetch, write : in bit;
bus_stats : out stats_type );
end component bus_monitor;
end package bus_monitor_pkg;
use work.bus_monitor_pkg.all;
entity bus_monitor is
generic ( verbose, dump_stats : boolean := false );
port ( mem_req, ifetch, write : in bit;
bus_stats : out stats_type );
end entity bus_monitor;
architecture general_purpose of bus_monitor is
begin
access_monitor : process is
variable access_count, ifetch_count,
write_count, read_count : natural := 0;
use std.textio;
variable L : textio.line;
begin
wait until mem_req = '1';
if ifetch = '1' then
ifetch_count := ifetch_count + 1;
if verbose then
textio.write(L, string'("Ifetch"));
textio.writeline(textio.output, L);
end if;
elsif write = '1' then
write_count := write_count + 1;
if verbose then
textio.write(L, string'("Write"));
textio.writeline(textio.output, L);
end if;
else
read_count := read_count + 1;
if verbose then
textio.write(L, string'("Read"));
textio.writeline(textio.output, L);
end if;
end if;
access_count := access_count + 1;
bus_stats.ifetch_freq <= real(ifetch_count) / real(access_count);
bus_stats.write_freq <= real(write_count) / real(access_count);
bus_stats.read_freq <= real(read_count) / real(access_count);
if dump_stats and access_count mod 5 = 0 then
textio.write(L, string'("Ifetch frequency = "));
textio.write(L, real(ifetch_count) / real(access_count));
textio.writeline(textio.output, L);
textio.write(L, string'("Write frequency = "));
textio.write(L, real(write_count) / real(access_count));
textio.writeline(textio.output, L);
textio.write(L, string'("Read frequency = "));
textio.write(L, real(read_count) / real(access_count));
textio.writeline(textio.output, L);
end if;
end process access_monitor;
end architecture general_purpose;
-- code from book (in text)
entity computer_system is
generic ( instrumented : boolean := false );
port ( -- . . . );
-- not in book
other_port : in bit := '0' );
-- end not in book
end entity computer_system;
-- end code from book
-- code from book
architecture block_level of computer_system is
-- . . . -- type and component declarations for cpu and memory, etc.
signal clock : bit; -- the system clock
signal mem_req : bit; -- cpu access request to memory
signal ifetch : bit; -- indicates access is to fetch an instruction
signal write : bit; -- indicates access is a write
-- . . . -- other signal declarations
begin
-- . . . -- component instances for cpu and memory, etc.
instrumentation : if instrumented generate
use work.bus_monitor_pkg;
signal bus_stats : bus_monitor_pkg.stats_type;
begin
cpu_bus_monitor : component bus_monitor_pkg.bus_monitor
port map ( mem_req, ifetch, write, bus_stats );
end generate instrumentation;
-- not in book
stimulus : process is
begin
ifetch <= '1'; write <= '0';
mem_req <= '1', '0' after 10 ns;
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '1'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '1'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '0'; write <= '1';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '1'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '0'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '1'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '0'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '1'; write <= '0';
wait for 20 ns;
mem_req <= '1', '0' after 10 ns;
ifetch <= '0'; write <= '0';
wait for 20 ns;
wait;
end process stimulus;
-- end not in book
end architecture block_level;
-- end code from book
|
