blob: 0ddddd90c8685d26866bbf0cb173d453eee9eac1 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity bottom is
port ( -- . . . );
--
port_name : in bit := '0' );
--
end entity bottom;
--------------------------------------------------
architecture bottom_arch of bottom is
signal bot_sig : -- . . .; -- 5
--
bit;
--
procedure proc ( -- . . . ) is
--
param_name : in bit := '0' ) is
--
variable v : -- . . .; -- 6
--
bit;
--
begin
-- . . .
--
report "--6: " & v'path_name;
report "--6: " & v'instance_name;
--
end procedure proc;
begin
delays : block is
constant d : integer := 1; -- 7
begin
-- . . .
--
assert false report "--7: " & d'path_name;
assert false report "--7: " & d'instance_name;
--
end block delays;
func : block is
begin
process is
variable v : -- . . .; -- 8
--
bit;
--
begin
-- . . .
--
report "--5: " & bot_sig'path_name;
report "--5: " & bot_sig'instance_name;
report "--8: " & v'path_name;
report "--8: " & v'instance_name;
proc(param_name => open);
wait;
--
--
end process;
end block func;
end architecture bottom_arch;
|
