1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
|
-- Copyright (C) 2001-2002 The University of Cincinnati.
-- All rights reserved.
-- This file is part of VESTs (Vhdl tESTs).
-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
-- By using or copying this Software, Licensee agrees to abide by the
-- intellectual property laws, and all other applicable laws of the U.S.,
-- and the terms of this license.
-- You may modify, distribute, and use the software contained in this
-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
-- June 1991. A copy of this license agreement can be found in the file
-- "COPYING", distributed with this archive.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: test184.ams,v 1.1 2002-03-27 22:11:20 paw Exp $
-- $Revision: 1.1 $
--
-- ---------------------------------------------------------------------
---------------------------------------------------------------------
----------------------------------------------------------------------
-- SIERRA REGRESSION TESTING MODEL
-- Develooped at:
-- Distriburted Processing Laboratory
-- University of Cincinnati
----------------------------------------------------------------------
-- File : test100.ams
-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
-- Created : Sept 2001
----------------------------------------------------------------------
-- Description :
----------------------------------------------------------------------
-- half wave Rectifier model ...
-- the test is done for checking the correct implementation
-- of the simultaneous if statement.it checks
-- nature declaration, terminal and quantity declarations.
----------------------------------------------------------------------
-- T1 diode D T2
-- o-----|>|-----o-------o The circuit comprises:
-- | | i) A diode .
-- ( ) >R=100ohms ii) A sinusoidal voltage source.
-- |Vs = 5sinwt > iii)A resistor R.
-- | >
-- |_____________|_______o
-- |gnd
-- -----
----------------------------------------------------------------------
PACKAGE electricalSystem IS
NATURE electrical IS real ACROSS real THROUGH;
FUNCTION SIN (X : real ) RETURN real;
FUNCTION EXP (X : real ) RETURN real;
END PACKAGE electricalSystem;
----------------------------------------------------------------------
USE work.electricalSystem.all;
ENTITY hwr IS
END hwr;
ARCHITECTURE ahwr OF hwr IS
terminal T1, T2 : electrical;
quantity VDiode across IDiode through T1 to T2;
quantity V2 across I2 through T2 to electrical'reference;
quantity VS across T1 to electrical'reference;
CONSTANT saturation_current : real := 0.0000000000001;
CONSTANT Vt : real := 0.025;
CONSTANT BV : real := 100.0;
CONSTANT neg_sat : real := -saturation_current;
BEGIN
--diode equations
if( vDiode >= (-1.0 * Vt)) USE
eq1: iDiode == saturation_current * (exp(vDiode/Vt) - 1.0);
ELSIF ((vDiode < (-3.0 * Vt)) AND (vDiode > -BV)) use
eq2: iDiode == neg_sat;
ELSE
eq3: iDiode == neg_sat * (exp(-(BV + vDiode)/Vt) - 1.0 +
saturation_current);
END USE ;
eqn2: v2 == 100.0 * i2;
eqn4: vs == 5.0 * sin(2.0 * 3.14 * 100000.0 *
real(time'pos(now)) * 1.0e-15 );
END ahwr ;
|
