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-- Copyright (C) 2001-2002 The University of Cincinnati.
-- All rights reserved.
-- This file is part of VESTs (Vhdl tESTs).
-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
-- By using or copying this Software, Licensee agrees to abide by the
-- intellectual property laws, and all other applicable laws of the U.S.,
-- and the terms of this license.
-- You may modify, distribute, and use the software contained in this
-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
-- June 1991. A copy of this license agreement can be found in the file
-- "COPYING", distributed with this archive.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: test168.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
-- $Revision: 1.1 $
--
-- ---------------------------------------------------------------------
----------------------------------------------------------------------
-- SIERRA REGRESSION TESTING MODEL
-- Develooped at:
-- Distriburted Processing Laboratory
-- University of Cincinnati
----------------------------------------------------------------------
-- File : test168.ams
-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
-- Created : Sept 2001
----------------------------------------------------------------------
-- Description :
----------------------------------------------------------------------
-- An RC model...
-- the test is done for checking the correct implementation
--of the simple simultaneous equation statement.it checks
--nature declaration, terminal, 'dot, 'integ and quantity declarations.
PACKAGE electricalSystem IS
NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
FUNCTION SIN(X : real) RETURN real;
FUNCTION EXP(X : real) RETURN real;
END PACKAGE electricalSystem;
use work.electricalSystem.all;
entity test is
end entity;
architecture atest of test is
terminal T1,T2, T3, T4:electrical;
quantity V1 across I1 through T1 to T2;
quantity V2 across I2 through T2 to T3;
quantity VC across IC through T3;
quantity VC1 across IC1 through T2 to T4;
quantity V3 across I3 through T4;
quantity VS across T1;
begin
e1: V1 == I1*1.0;
e2: V2 == I2*1.0;
e3: V3 == I3*10.0;
e4: VC == IC'integ*1.0e12;
e5: VC1 == IC1'integ*1.0e12;
esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
end architecture atest;
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