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-- Copyright (C) 2000-2002 The University of Cincinnati.
-- All rights reserved.
-- This file is part of VESTs (Vhdl tESTs).
-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
-- By using or copying this Software, Licensee agrees to abide by the
-- intellectual property laws, and all other applicable laws of the U.S.,
-- and the terms of this license.
-- You may modify, distribute, and use the software contained in this
-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
-- June 1991. A copy of this license agreement can be found in the file
-- "COPYING", distributed with this archive.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: test156.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
-- $Revision: 1.1 $
--
-- ---------------------------------------------------------------------
-- check the implemetatio of ports and generics.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity inv is
port (
x : in bit;
xout : out bit);
end inv;
architecture inverter of inv is
begin
xout <= not x after 100ns ;
end inverter ;
PACKAGE electricalSystem IS
NATURE electrical IS real ACROSS real THROUGH GROUND reference;
FUNCTION SIN (X : real ) RETURN real;
FUNCTION EXP (X : real ) RETURN real;
END PACKAGE electricalSystem;
use work.electricalSystem.all;
entity resistor is
generic ( res : real := 10.0 ) ;
port (terminal P, N : electrical );
end resistor;
architecture behav of resistor is
quantity VPTON across IPTON through P to N;
begin
res1 : VPTON == IPTON * res ;
end behav;
use work.electricalSystem.all;
ENTITY circuit1 IS
END circuit1;
ARCHITECTURE behavior OF circuit1 IS
component inv is
port (
x : in bit;
xout : out bit);
end component ;
for all : inv use entity work.inv(inverter) ;
component resistor is
generic ( res : real := 10.0 ) ;
port (terminal P, N : electrical );
end component;
for all : resistor use entity work.resistor(behav);
terminal n1,n2 : electrical;
QUANTITY vIn ACROSS iIn THROUGH n1 ;
signal y:bit:='0';
BEGIN
D2 : inv port map(x=>y, xout=>y);
testbench:PROCESS
BEGIN
WAIT ON y;
END PROCESS;
R1 : resistor generic map ( res => 500.0) port map (P => n1, N => n2);
R2 : resistor port map (P => n2, N => ground);
vsource: vIn == 5.0 * sin(2.0 * 3.14 * 100000.0 * real(time'pos(now)) * 1.0e-15);
END ARCHITECTURE behavior;
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