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-- Copyright (C) 2001-2002 The University of Cincinnati.
-- All rights reserved.
-- This file is part of VESTs (Vhdl tESTs).
-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
-- By using or copying this Software, Licensee agrees to abide by the
-- intellectual property laws, and all other applicable laws of the U.S.,
-- and the terms of this license.
-- You may modify, distribute, and use the software contained in this
-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
-- June 1991. A copy of this license agreement can be found in the file
-- "COPYING", distributed with this archive.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: test154.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
-- $Revision: 1.1 $
--
-- ---------------------------------------------------------------------
----------------------------------------------------------------------
-- SIERRA REGRESSION TESTING MODEL
-- Develooped at:
-- Distriburted Processing Laboratory
-- University of Cincinnati
-- Cincinnati
----------------------------------------------------------------------
-- File : test154.ams
-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
-- Created : Sept 2001
----------------------------------------------------------------------
-- Description :
----------------------------------------------------------------------
-- A simple model which has a voltage source.
-- The output voltage Vout is dependent on the value of VS wrt Vref
-- If the voltage is below Vref, the output is a 0 else output is a 1.
-- the test is done for checking the correct implementation
--of the simple simultaneous if statement.it checks
--nature declaration, terminal and quantity declarations.
PACKAGE electricalSystem IS
NATURE electrical IS real ACROSS real THROUGH ground reference;
FUNCTION SIN(X : real) RETURN real;
FUNCTION EXP(X : real) RETURN real;
END PACKAGE electricalSystem;
use work.electricalSystem.all;
entity test is
end entity;
architecture atest of test is
terminal T1,T2:electrical;
quantity VS across T1;
quantity Vout: real;
constant Vref:real:=5.0;
begin
esource: VS == 5.0;
if (VS<=Vref) use
e1: Vout == 1.0;
else
e2: Vout == 0.0;
end use;
end architecture atest;
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