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-- Copyright (C) 2001-2002 The University of Cincinnati.
-- All rights reserved.
-- This file is part of VESTs (Vhdl tESTs).
-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
-- By using or copying this Software, Licensee agrees to abide by the
-- intellectual property laws, and all other applicable laws of the U.S.,
-- and the terms of this license.
-- You may modify, distribute, and use the software contained in this
-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
-- June 1991. A copy of this license agreement can be found in the file
-- "COPYING", distributed with this archive.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: test148.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
-- $Revision: 1.1 $
--
-- ---------------------------------------------------------------------
----------------------------------------------------------------------
-- SIERRA REGRESSION TESTING MODEL
-- Develooped at:
-- Distriburted Processing Laboratory
-- University of cincinnati
-- Cincinnati
----------------------------------------------------------------------
-- File : test148.ams
-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
-- Created : Sept 2001
----------------------------------------------------------------------
-- Description :
----------------------------------------------------------------------
-- the test checks for the correctness of the quantity, terminal, nature
-- and package declarations. the terminals are assigned as terminals.
-- a simple V-R circuit is considered.
-----------------------------------------------------------------------
PACKAGE electricalsystem IS
FUNCTION SIN(X : real) RETURN real;
FUNCTION EXP(X : real) RETURN real;
FUNCTION SQRT(X : real) RETURN real;
FUNCTION POW(X,Y : real) RETURN real;
-- SUBTYPE voltage IS real;
-- SUBTYPE current IS real;
NATURE electrical IS real ACROSS real THROUGH ground reference;
END PACKAGE electricalsystem;
use work.electricalsystem.all;
ENTITY test IS
generic(ampl:real:=5.0);
PORT (TERMINAL p: electrical);
END ENTITY test;
ARCHITECTURE sine OF test IS
constant freq: real:=10000.0;
QUANTITY v ACROSS i THROUGH p;
quantity vr across ir through p;
BEGIN
e1: v == ampl * sin(2.0 * 3.14159 * freq * real(time'pos(now))*1.0e-12);
e2: vr== ir*10.0;
END ARCHITECTURE sine;
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