1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
|
-- Copyright (C) 2001-2002 The University of Cincinnati.
-- All rights reserved.
-- This file is part of VESTs (Vhdl tESTs).
-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
-- By using or copying this Software, Licensee agrees to abide by the
-- intellectual property laws, and all other applicable laws of the U.S.,
-- and the terms of this license.
-- You may modify, distribute, and use the software contained in this
-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
-- June 1991. A copy of this license agreement can be found in the file
-- "COPYING", distributed with this archive.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: test137.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
-- $Revision: 1.1 $
--
-- ---------------------------------------------------------------------
----------------------------------------------------------------------------
-- SIERRA REGRESSION TESTING MODEL
-- Develooped at:
-- Distriburted Processing Laboratory
-- University of cincinnati
-- Cincinnati
----------------------------------------------------------------------------
-- File : test137.ams
-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
-- Created : May 2001
-----------------------------------------------------------------------------
-- Description :
-----------------------------------------------------------------------------
-- the test cheks the correctness of the electrical_vector.array of terminals
-- also the use of real vectors.. array of real values.
-- the circuit is a weighted summer the output is available at the
-- ooutput terminal o.
-- LRM 4.3.2
-------------------------------------------------------------------------------
PACKAGE electricalSystem IS
NATURE electrical IS real ACROSS real THROUGH ground reference;
FUNCTION SIN(X : real) RETURN real;
FUNCTION EXP(X : real) RETURN real;
FUNCTION SQRT(X : real) RETURN real;
FUNCTION POW(X,Y : real) RETURN real;
TYPE real_vector is array(0 to 3) of real;
TYPE electrical_vector is array(0 to 3) of electrical;
END PACKAGE electricalSystem;
use work.electricalSystem.all;
entity test is
generic (beta,gamma : real_vector);
port(terminal inp, inm: electrical_vector;
terminal o: electrical);
end entity;
architecture atest of test is
--TYPE real_vector is array(0 to 3) of real;
--TYPE electrical_vector is array(0 to 3) of electrical;
quantity vp across ip through inp to electrical'reference;
quantity vm across inm to electrical'reference;
quantity vo across io through o to electrical'reference;
variable bvs, gvs : real:=0.0;
function "*" (a:real_vector;
b: electrical_vector'across)
return real is
variable result : real:=0.0;
begin
for i in (0 to 3) loop
result:= result+ a(i)*b(i);
end loop;
return result;
end function "*";
begin
vo== beta*vp - gamma*vm;
end architecture atest;
use work.electricalSystem.all;
entity tb is
end entity;
architecture atb of tb is
signal myvec1,myvec2:real_vector(0 to 3);
signal myinput1, myinput2: electrical_vector(0 to 3);
terminal tinp, tinm: electrical_vector;
terminal to: electrical;
component test
port(terminal inp, inm: electrical_vector;
terminal o: electrical);
end component test;
for all: test use entity work.test(atest);
begin
unit: test port map(tinp,tinm, to, electrical'reference);
a_process: process
begin
myvec1 == 1.0;
myinput1 == 1.0;
myvec2 == 2.0;
myinput2 == 2.0;
wait for 10 ns;
myvec1 == 1.0;
myinput1 == 1.0;
myvec2 == 2.0;
myinput2 == 2.0;
wait for 10 ns;
myvec1 == 1.0;
myinput1 == 2.0;
myvec2 == 2.0;
myinput2 == 1.0;
wait for 10 ns;
myvec1 == 1.0;
myinput1 == 2.0;
myvec2 == 2.0;
myinput2 == 1.0;
wait for 10 ns;
end process;
end atb;
|
