1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
|
-- Copyright (C) 2000-2002 The University of Cincinnati.
-- All rights reserved.
-- This file is part of VESTs (Vhdl tESTs).
-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
-- By using or copying this Software, Licensee agrees to abide by the
-- intellectual property laws, and all other applicable laws of the U.S.,
-- and the terms of this license.
-- You may modify, distribute, and use the software contained in this
-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
-- June 1991. A copy of this license agreement can be found in the file
-- "COPYING", distributed with this archive.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: test110.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
-- $Revision: 1.1 $
--
-- ---------------------------------------------------------------------
-- an example of a model having both a signal assignment statement
-- as well as a simple simultaneous statement.
PACKAGE electricalSystem IS
NATURE electrical IS real ACROSS real THROUGH GROUND reference;
FUNCTION SIN (X : real ) RETURN real;
FUNCTION EXP (X : real ) RETURN real;
END PACKAGE electricalSystem;
use work.electricalSystem.all;
use std.textio.all;
ENTITY test IS
END test;
ARCHITECTURE behavior OF test IS
CONSTANT r1 : real := 100.0; -- value of R1
terminal t1 : electrical;
QUANTITY vIn ACROSS t1;
QUANTITY vR ACROSS iR THROUGH t1 ;
signal y:bit:='0';
BEGIN
process(y)
begin
y <= not(y) after 1000 ns;
end process;
testbench:PROCESS
BEGIN
WAIT ON y;
END PROCESS;
res_stmt1: vR == iR * r1 ;
vsource: vIn == 5.0 * sin(2.0 * 3.14 * 100000.0 * real(time'pos(now)) * 1.0e-15);
END ARCHITECTURE behavior;
|
