testsuite/vests/vhdl-93/clifton-labs/compliant/functional/entities/pass-integer-through-inout-port.vhdl


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entity test_output is
  port (
    output : inout integer := 10
    );
end test_output;

architecture only of test_output is
begin  -- test_output
  test: process
  begin  -- process test
    assert output = 10 report "test failed" severity error;
    assert output /= 10 report "test passed" severity note;
    wait;
  end process test;
end only;