testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/signal/simple-last-value.vhdl


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

entity test is
end test;

architecture only of test is
  signal s : bit := '0';
begin
  p : process
  begin
    s <= '1';
    wait for 0 fs;
    assert s'last_value = '0' report "TEST FAILED" severity failure;
    report "TEST PASSED";
    wait;
  end process;
end only;