blob: 1cc46da8d3757b76531f41733c138227b93c3161 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1189.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p03n01i01189ent IS
END c08s01b00x00p03n01i01189ent;
ARCHITECTURE c08s01b00x00p03n01i01189arch OF c08s01b00x00p03n01i01189ent IS
signal k : integer := 0;
BEGIN
TESTING: PROCESS
BEGIN
k <= 5 after 5 ns;
wait on ii;
assert FALSE
report "***FAILED TEST: c08s01b00x00p03n01i01189 - Undefined signal in sensitivity list."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p03n01i01189arch;
|
