blob: fa3a0eddc03398f182b8de3ba9d117144d824cbd (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc765.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x02p06n01i00765ent_a IS
port ( c1 : in integer ;
c2 : out integer );
END c01s01b01x02p06n01i00765ent_a;
ARCHITECTURE c01s01b01x02p06n01i00765arch_a OF c01s01b01x02p06n01i00765ent_a IS
BEGIN
c2 <= c1;
END c01s01b01x02p06n01i00765arch_a;
ENTITY c01s01b01x02p06n01i00765ent IS
port ( p1 : in integer ;
p2 : out integer );
END c01s01b01x02p06n01i00765ent;
ARCHITECTURE c01s01b01x02p06n01i00765arch OF c01s01b01x02p06n01i00765ent IS
component c01s01b01x02p06n01i00765ent_b
port ( c1 : in integer ;
c2 : out integer );
end component;
for L : c01s01b01x02p06n01i00765ent_b use entity work.c01s01b01x02p06n01i00765ent_a(c01s01b01x02p06n01i00765arch_a);
BEGIN
L: c01s01b01x02p06n01i00765ent_b
port map (p1, p2); -- Success_here
-- The formal c1 is of mode in and
-- The corresponding actual p1 is of
-- mode in which is legal.
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s01b01x02p06n01i00765"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s01b01x02p06n01i00765arch;
|
