blob: 4bfd50e0a6e5564d58a8ec4b23a74f67aadac8bd (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1975.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p02n02i01975ent IS
constant T:bit := '1';
constant F:bit := '0';
END c07s02b01x00p02n02i01975ent;
ARCHITECTURE c07s02b01x00p02n02i01975arch OF c07s02b01x00p02n02i01975ent IS
BEGIN
TESTING: PROCESS
variable A1 : bit := T;
variable A2 : bit := F;
BEGIN
assert NOT( (A1 and A1) = '1' and
(A1 and A2) = '0' and
(A2 and A1) = '0' and
(A2 and A2) = '0' and
(A1 or A1) = '1' and
(A1 or A2) = '1' and
(A2 or A1) = '1' and
(A2 or A2) = '0' and
(A1 xor A1) = '0' and
(A1 xor A2) = '1' and
(A2 xor A1) = '1' and
(A2 xor A2) = '0' and
(A1 nand A1) = '0' and
(A1 nand A2) = '1' and
(A2 nand A1) = '1' and
(A2 nand A2) = '1' and
(A1 nor A1) = '0' and
(A1 nor A2) = '0' and
(A2 nor A1) = '0' and
(A2 nor A2) = '1' and
(not A1) = '0' and
(not A2) = '1')
report "***PASSED TEST: c07s02b01x00p02n02i01975"
severity NOTE;
assert ( (A1 and A1) = '1' and
(A1 and A2) = '0' and
(A2 and A1) = '0' and
(A2 and A2) = '0' and
(A1 or A1) = '1' and
(A1 or A2) = '1' and
(A2 or A1) = '1' and
(A2 or A2) = '0' and
(A1 xor A1) = '0' and
(A1 xor A2) = '1' and
(A2 xor A1) = '1' and
(A2 xor A2) = '0' and
(A1 nand A1) = '0' and
(A1 nand A2) = '1' and
(A2 nand A1) = '1' and
(A2 nand A2) = '1' and
(A1 nor A1) = '0' and
(A1 nor A2) = '0' and
(A2 nor A1) = '0' and
(A2 nor A2) = '1' and
(not A1) = '0' and
(not A2) = '1')
report "***FAILED TEST: c07s02b01x00p02n02i01975 - BIT type truth table test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p02n02i01975arch;
|
