blob: 24214d8f9f9cce30ee46c6b4d41af3b1f52d54d7 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1735.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s04b00x00p06n01i01735ent IS
END c09s04b00x00p06n01i01735ent;
ARCHITECTURE c09s04b00x00p06n01i01735arch OF c09s04b00x00p06n01i01735ent IS
signal arch_s1 : bit;
signal arch_s2 : boolean;
signal arch_s3 : character;
signal arch_s4 : severity_level;
signal arch_s5 : integer;
signal arch_s6 : real;
signal arch_s7 : time;
signal arch_s8 : positive;
signal arch_s9 : natural;
BEGIN
ASSERT arch_s1 /= bit'left
REPORT "bit concurrent assertion"
severity NOTE;
ASSERT arch_s2 /= boolean'left
REPORT "boolean concurrent assertion"
severity NOTE;
ASSERT arch_s3 /= character'left
REPORT "character concurrent assertion"
severity NOTE;
ASSERT arch_s4 /= severity_level'left
REPORT "severity_level concurrent assertion"
severity NOTE;
ASSERT arch_s5 /= integer'left
REPORT "integer concurrent assertion"
severity NOTE;
ASSERT arch_s6 /= real'left
REPORT "real concurrent assertion"
severity NOTE;
ASSERT arch_s7 /= time'left
REPORT "time concurrent assertion"
severity NOTE;
ASSERT arch_s8 /= positive'left
REPORT "positive concurrent assertion"
severity NOTE;
ASSERT arch_s9 /= natural'left
REPORT "natural concurrent assertion"
severity NOTE;
TESTING: PROCESS
BEGIN
ASSERT arch_s1 /= bit'left
REPORT "bit concurrent assertion"
severity NOTE;
ASSERT arch_s2 /= boolean'left
REPORT "boolean concurrent assertion"
severity NOTE;
ASSERT arch_s3 /= character'left
REPORT "character concurrent assertion"
severity NOTE;
ASSERT arch_s4 /= severity_level'left
REPORT "severity_level concurrent assertion"
severity NOTE;
ASSERT arch_s5 /= integer'left
REPORT "integer concurrent assertion"
severity NOTE;
ASSERT arch_s6 /= real'left
REPORT "real concurrent assertion"
severity NOTE;
ASSERT arch_s7 /= time'left
REPORT "time concurrent assertion"
severity NOTE;
ASSERT arch_s8 /= positive'left
REPORT "positive concurrent assertion"
severity NOTE;
ASSERT arch_s9 /= natural'left
REPORT "natural concurrent assertion"
severity NOTE;
assert FALSE
report "***PASSED TEST: c09s04b00x00p06n01i01735 - This need manual check - The concurrent assertion statement and the sequential assertion should print out the same ASSERTION NOTES."
severity NOTE;
wait;
END PROCESS TESTING;
END c09s04b00x00p06n01i01735arch;
|
