blob: 4679ace7c95f609d3d5e94fb92cc99d2ce8a58c8 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc171.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b03x01p03n01i00171ent IS
port (ABus : in bit;
DBus : out bit;
MemReq : in bit;
BusReq : inout bit;
BusAck : buffer bit;
DataRdy : linkage bit);
constant Board : integer := 7 ;
END c04s03b03x01p03n01i00171ent;
ARCHITECTURE c04s03b03x01p03n01i00171arch OF c04s03b03x01p03n01i00171ent IS
alias SIGN1 : bit is BusReq; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c04s03b03x01p03n01i00171"
severity NOTE;
wait;
END PROCESS TESTING;
END c04s03b03x01p03n01i00171arch;
|
