blob: bf1cef7e3731dded12d0808210d2638fb13f15a6 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
|
library ieee;
use ieee.std_logic_1164.all;
entity works is
generic (
width : integer := 8
);
port(
x : in std_logic;
y : out std_logic_vector(width-1 downto 0);
z : out std_logic
);
end works;
architecture a of works is
component subcomponent is
generic (
w : integer
);
port(
x : in std_logic;
y : out std_logic_vector(w-1 downto 0)
);
end component;
begin
s : subcomponent
generic map(
w => width+1
)
port map(
x => x,
y(8 downto 1) => y,
y(0) => z
);
end a;
|
