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VHDL 2008/93/87 simulator
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trans-chap4.adb
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2015-12-18
Pass signal values to interfaces. 'sigptr' optimization.
Tristan Gingold
Improve simulation speed by about 20%.
2015-09-04
Suppress stack switching; save process state in secondary stack.
Tristan Gingold
2015-09-03
Adjust previous patch (destroy types for default port values).
Tristan Gingold
2015-09-02
Translate: explicitly clean transient types.
Tristan Gingold
2015-09-01
Destroy types of default generic values.
Tristan Gingold
2015-08-29
Replace fat accesses by bounds accesses
Tristan Gingold
translate: separate info for signals from object. Improve some error messages.
2015-06-05
Rework procedure calls, now use a record to pass parameters.
Tristan Gingold
2015-05-27
Handle signal attribute in declarations. Fix alias of implicit signal.
Tristan Gingold
2015-01-10
Handle overflow during evaluation of type conversion. Forward on 'image.
Tristan Gingold
2014-12-29
Rework string literals: store literals position.
Tristan Gingold
2014-12-15
Use same node for implicit and explicit subprogram declarations.
Tristan Gingold
2014-11-11
Create_Range_From_Length: use Mnode instead of ptr. Style changes.
Tristan Gingold
2014-11-09
Split translation into child packages.
Tristan Gingold