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AgeCommit message (Expand)Author
2014-09-25Add a python script to automatically generate disp_tree.Tristan Gingold
2014-09-02Keep names in the tree.Tristan Gingold
2014-06-28Resolve expression in variable assignment when target is an aggregate.Tristan Gingold
2014-06-24Use library unit instead of design unit.Tristan Gingold
2013-12-17Sync tree: add parsing of AMS-VHDL, add Darwin syntax in asm files.Tristan Gingold
2010-01-12ghdl 0.29 release.gingold
2008-09-06New feature: all-sensitized processes (for vhdl 2008)gingold
2006-10-02direct drivers and bugs fixgingold
2005-09-24First import from sourcesgingold