6 files changed, 132 insertions, 0 deletions
diff --git a/testsuite/gna/bug22868/Makefile b/testsuite/gna/bug22868/Makefile
new file mode 100644
index 0000000..328c08c
--- /dev/null
+++ b/testsuite/gna/bug22868/Makefile
@@ -0,0 +1,15 @@
+.PHONY: default
+default:
+	-make works.o
+	-make fails1.o
+	-make fails2.o
+
+
+%.o: %.vhdl
+	ghdl -a $<
+
+.PHONY: clean
+clean:
+	ghdl --clean
+	rm *.cf
+
diff --git a/testsuite/gna/bug22868/NOTES b/testsuite/gna/bug22868/NOTES
new file mode 100644
index 0000000..bef1471
--- /dev/null
+++ b/testsuite/gna/bug22868/NOTES
@@ -0,0 +1,9 @@
+I think these are the most stripped down examples I could figure out,
+and the gist of it seems to be that it has to do with splitting the
+right hand side of a port map by amounts that are not known at
+elaboration time...or something like that. In fails2.vhdl the
+variable isn't declared anywhere, but it still crashes with the
+bug notice, rather than just failing with an error message.
+
+works.vhdl is provided for contrast, i.e. generics are used
+except for the specific line that would cause it to crash.
diff --git a/testsuite/gna/bug22868/fails1.vhdl b/testsuite/gna/bug22868/fails1.vhdl
new file mode 100644
index 0000000..7bd3a91
--- /dev/null
+++ b/testsuite/gna/bug22868/fails1.vhdl
@@ -0,0 +1,31 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity fails1 is
+	generic (
+		w : integer := 8
+	);
+	port(
+		x : in std_logic;
+		y : out std_logic_vector(7 downto 0);
+		z : out std_logic
+	);
+end entity;
+
+architecture a of fails1 is
+	component subcomponent is
+		port(
+			x : in std_logic;
+			y : out std_logic_vector(8 downto 0)
+		);
+	end component;
+begin
+
+	s : subcomponent
+	port map(
+		x => x,
+		y(w downto 1) => y,
+		y(0) => z
+	);
+
+end a;
diff --git a/testsuite/gna/bug22868/fails2.vhdl b/testsuite/gna/bug22868/fails2.vhdl
new file mode 100644
index 0000000..57819f9
--- /dev/null
+++ b/testsuite/gna/bug22868/fails2.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity fails2 is
+	port(
+		x : in std_logic;
+		y : out std_logic_vector(7 downto 0);
+		z : out std_logic
+	);
+end fails2;
+
+architecture a of fails2 is
+	component subcomponent is
+		port(
+			x : in std_logic;
+			y : out std_logic_vector(8 downto 0)
+		);
+	end component;
+begin
+
+	s : subcomponent
+	port map(
+		x => x,
+		y(cheese downto 1) => y,
+		y(0) => z
+	);
+
+end a;
diff --git a/testsuite/gna/bug22868/testsuite.sh b/testsuite/gna/bug22868/testsuite.sh
new file mode 100755
index 0000000..6b3dc4f
--- /dev/null
+++ b/testsuite/gna/bug22868/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze_failure fails1.vhdl
+analyze_failure fails2.vhdl
+analyze works.vhdl
+clean
+
+echo "Test successful"
diff --git a/testsuite/gna/bug22868/works.vhdl b/testsuite/gna/bug22868/works.vhdl
new file mode 100644
index 0000000..bf1cef7
--- /dev/null
+++ b/testsuite/gna/bug22868/works.vhdl
@@ -0,0 +1,39 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity works is
+	generic (
+		width : integer := 8
+	);
+	port(
+		x : in std_logic;
+		y : out std_logic_vector(width-1 downto 0);
+		z : out std_logic
+	);
+end works;
+
+architecture a of works is
+	component subcomponent is
+		generic (
+			w : integer
+		);
+		port(
+			x : in std_logic;
+			y : out std_logic_vector(w-1 downto 0)
+		);
+	end component;
+begin
+
+	s : subcomponent
+	generic map(
+		w => width+1
+	)
+	port map(
+		x => x,
+		y(8 downto 1) => y,
+		y(0) => z
+	);
+
+end a;
+
+