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diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_counter.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_counter.vhd
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+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_counter is
+end entity tb_counter;
+
+
+use work.counter_types.all;
+
+architecture test of tb_counter is
+
+  signal clk, clr : bit := '0';
+  signal q0, q1 : digit;
+
+begin
+
+  dut : entity work.counter(registered)
+    port map ( clk => clk, clr => clr,
+               q0 => q0, q1 => q1 );
+
+  clk_gen : clk <= not clk after 20 ns;
+
+  clr_gen : clr <= '1' after 95 ns,
+		   '0' after 135 ns;
+
+end architecture test;