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diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inductor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inductor.vhd
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+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity inductor is
+  port (terminal n1, n2: electrical);
+end entity inductor;
+
+----------------------------------------------------------------
+
+architecture ideal of inductor is
+  constant L: inductance := 0.5;
+  quantity branch_voltage across branch_current through n1 to n2;
+begin
+  branch_voltage == L* branch_current'dot;
+end architecture ideal;